Nios II Lab 1


The purpose of this lab is to learn how to create and use a simple reconfigurable computer system. The system will consist of an Altera Nios II processor and an application program. You will use the Quartus II and SOPC Builder software to generate the hardware portion of the system. You will use the Altera Nios II IDE software to compile, load and run the application program.


Part I: Building the System

First, you will use the SOPC Builder to create a system consisting of a Nios II/f processor, an on-chip memory block, a JTAG UART, an interval timer, and a parallel I/O interface..

Implement the system as follows:

  1. Create a new Quartus II project. Select Cyclone II EP2C35F672C6 as the target chip, which is the FPGA chip on the Altera DE2 board.

  2. Use the SOPC Builder to create a system named cpu1, which includes the following components:
    • Nios II/f processor with JTAG Debug Module Level 1
    • On-chip memory - RAM mode and 32 Kbytes in size with width of 32
    • Interval timer
    • PIO interface, both read and write lines, 32-bit width.
    • JTAG UART bits

  3. From the System menu, select Auto-Assign Base Addresses, then select Auto-Assign IRQ settings

  4. Generate the system, then exit the SOPC Builder to return to the Quartus II software.

  5. A prototype top-level module and 7-segment interface are provided in the lab download zip file. Add these Verilog files and those generated by the SOPC tool into the project and make nios2lab.v the top-level module. Check the module name and parameter list generated by SOPC with the values assumed in nios2lab.v. Edit the file nios2lab.v, if necessary, to agree with the names assigned by the SOPC tool.

  6. Assign the pin connections by importing them from DE2_pin_assignments.csv.

  7. Compile the Quartus II project.

  8. Program and configure the Cyclone II FPGA on the DE2 Board to implement the generated system. To use the system, we have to give the processor a program to execute, which will we do in Part II of this lab.

See the documentation from the Quartus compilation: nios2lab1 document

Part II: Programming the System

To create a simple Hello World project, perform the following steps:

  1. Start the Altera Nios II IDE software.

  2. On the File menu, click the New, C/C++ Application. Set the location to the same path as the hardware project. Choose cpu1.ptf as the target hardware. Choose Hello World Small as the template.

  3. Click Finish to create a project named hello_world_small_0. This process also creates a system library project named hello_world_small_0_syslib.

  4. In the C/C++ Projects view on the left, right-click the hello_world_small_0 project and choose Build Project

When the build finishes, the Console view at the bottom of the workbench displays the message "Build completed." If the Console view is not visible, click the Console tab.

To download executable code to the Nios development board do the following:

  1. On the Run menu, click Run ... The Run dialog box opens.

  2. Select Nios II Hardware in the Configurations list.

  3. Click New

  4. Click the Target Connection tab.

See: program source

Sample dialog screens


When you start the SOPC ("System on a Programmable Chip") tool, you get the following dialog.

Selecting a processor brings up the following dialog:

This next dialog adds On-Chip Memory:

The next dialog adds an Interval Timer:

Here is the dialog for a PIO unit. Note that a port width of 32-bits is selected and both input and output ports are selected.

The JTAG UART provides serial communication between the board and the host computer (through a console window within the IDE).

The completed SOPC tool dialog page summarizes the configured system.

Here is the system generation dialog window:


Finally, here are the dialogs from choosing a NIOS II IDE project:

Maintained by John Loomis, last updated 2 Sept 2008