Ethernet Network Controller

The DE2 board provides Ethernet support via the Davicom DM9000A Fast Ethernet controller chip. The DM9000A includes a general processor interface, 16 Kbytes SRAM, a media access control (MAC) unit, and a 10/100M PHY transceiver. Figure 1 shows the schematic for the Fast Ethernet interface, and the associated pin assignments are listed in Table 1. For detailed information on how to use the DM9000A refer to its datasheet and application note, which are available on the manufacturer’s web site, and from the references below.

Figure 1. Schematic diagram of the Fast Ethernet DM9000A chip.

Table 1. Fast Ethernet signal assignments.

Signal NameDescription
ENET_DATA[15:0] DM9000A DATA[15:0]
ENET_CLK DM9000A Clock 25 MHz
ENET_CMD DM9000A Command/Data Select, 0 = Command, 1 = Data
ENET_CS_N DM9000A Chip Select
ENET_INT DM9000A Interrupt
ENET_RD_N DM9000A Read
ENET_WR_N DM9000A Write
ENET_RST_N DM9000A Reset

See DE2_pin_assignments.csv, a comma-delimited file that matches "standard" descriptive names to actual FPGA pin locations. This file can be directly opened in Microsoft Excel.

References

   DM9000A datasheet (pdf) and application notes (pdf).

   DE2 User Manual, version 1.4, 2006. (pdf)


Maintained by John Loomis, last updated 18 April 2007