Download: project files
Verilog source and Quartus reports
DE2 Board Audio CODEC
The chip system clock is programmed for 384 fs = 18.434 MHz with a sampling frequency fs = 48 kHz. The bit clock must run at 32 fs, and the LR clock at fs, one channel is available at the rising edge and the other at the falling edge. The bit clock runs at 1/12 of the system clock.
Maintained by John Loomis, last updated 11 January 2008