Altera DE2 Project Diglab3

Download: design files

This lab implements a timer. KEY3 starts and stops the timer. KEY0 resets the count (and stops the timer)


Top-level Module

Setup state variable and counters

reg state;
wire clock, reset, pulse;

Make a 4-digit ripple decimal counter

wire [3:0] digit3, digit2, digit1, digit0;
wire [3:0] ovr;
decimal_counter count0(digit0,ovr[0],clock,reset);
decimal_counter count1(digit1,ovr[1],ovr[0],reset);
decimal_counter count2(digit2,ovr[2],ovr[1],reset);
decimal_counter count3(digit3,ovr[3],ovr[2],reset);

Map to 7-segment displays

hex_7seg dsp0(digit0,HEX0);
hex_7seg dsp1(digit1,HEX1);
hex_7seg dsp2(digit2,HEX2);
hex_7seg dsp3(digit3,HEX3);

Use a gated clock to control the counter

assign clock = (state? myclock[2]: 1'b0);
assign reset = (~pulse & RST);

Use a oneshot to trigger reset signal. This sets the count to zero on the first clock pulse after counting starts.

oneshot pulser(

State machine: KEY3 or KEY0 changes the state.

always @ (negedge KEY[3] or negedge RST)
    if (!RST) state <= 1'b0;
    else state <= ~state;

Map state/reset signals to green LEDs

assign LEDG[0] = ~RST;
assign LEDG[1] = state;
assign LEDG[8:2] = 6'h00;


The one-shot is a monostable pulser. When the trigger signal goes high, the output pulse is set high for one clock cycle. Another output pulse can not occur until the trigger undergoes another positive edge transistion.

module oneshot(output reg pulse_out, input trigger_in, input clk);
reg delay;

always @ (posedge clk)
    if (trigger_in && !delay) pulse_out <= 1'b1;
    else pulse_out <= 1'b0;
    delay <= trigger_in;


Verilog source and Quartus compilation report

Maintained by John Loomis, last updated 20 January 2008