diglab3.v
module diglab3( // Clock Input (50 MHz) input CLOCK_50, // Push Buttons input [3:0] KEY, // DPDT Switches input [17:0] SW, // 7-SEG Displays output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, // LEDs output [8:0] LEDG, // LED Green[8:0] output [17:0] LEDR, // LED Red[17:0] // GPIO Connections inout [35:0] GPIO_0, GPIO_1 ); // All inout port turn to tri-state assign GPIO_0 = 36'hzzzzzzzzz; assign GPIO_1 = 36'hzzzzzzzzz; wire RST; assign RST = KEY[0]; // Setup clock divider wire [6:0] myclock; clock_divider cdiv(CLOCK_50,RST,myclock); // Send switches to red leds assign LEDR = SW; // Blank the unused HEX displays assign HEX7 = 7'h7f; assign HEX6 = 7'h7f; assign HEX5 = 7'h7f; assign HEX4 = 7'h7f; // state variable reg state; // set up counters wire [3:0] digit3, digit2, digit1, digit0; wire [3:0] ovr; wire clock, reset, pulse; assign clock = (state? myclock[2]: 1'b0); assign reset = (~pulse & RST); decimal_counter count0(digit0,ovr[0],clock,reset); decimal_counter count1(digit1,ovr[1],ovr[0],reset); decimal_counter count2(digit2,ovr[2],ovr[1],reset); decimal_counter count3(digit3,ovr[3],ovr[2],reset); // map to 7-segment displays hex_7seg dsp0(digit0,HEX0); hex_7seg dsp1(digit1,HEX1); hex_7seg dsp2(digit2,HEX2); hex_7seg dsp3(digit3,HEX3); // use one-pulse to trigger reset oneshot pulser( .pulse_out(pulse), .trigger_in(state), .clk(CLOCK_50) ); always @ (negedge KEY[3] or negedge RST) begin if (!RST) state <= 1'b0; else state <= ~state; end // map state to green LEDs assign LEDG[0] = ~RST; assign LEDG[1] = state; assign LEDG[8:2] = 6'h00; endmodule
decimal_counter.v
module decimal_counter(A,OVERFLOW,CLK,RST); input CLK, RST; output OVERFLOW; output [3:0] A; reg OVERFLOW; reg [3:0] A; always @ (posedge CLK or negedge RST) if (~RST) begin OVERFLOW <= 1'b0; A <= 4'b0000; end else if (A<9) begin A <= A + 1'b1; OVERFLOW <= 1'b0; end else begin A <= 4'b0000; OVERFLOW <= 1'b1; end endmodule
clock_divider.v
module clock_divider(CLK,RST,clock); input CLK,RST; output [6:0] clock; wire clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz; assign clock = {clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz}; divide_by_50 d6(clk_1Mhz,CLK,RST); divide_by_10 d5(clk_100Khz,clk_1Mhz,RST); divide_by_10 d4(clk_10Khz,clk_100Khz,RST); divide_by_10 d3(clk_1Khz,clk_10Khz,RST); divide_by_10 d2(clk_100hz,clk_1Khz,RST); divide_by_10 d1(clk_10hz,clk_100hz,RST); divide_by_10 d0(clk_1hz,clk_10hz,RST); endmodule
divide_by_10.v
module divide_by_10(Q,CLK,RST); input CLK, RST; output Q; reg Q; reg [2:0] count; always @ (posedge CLK or negedge RST) begin if (~RST) begin Q <= 1'b0; count <= 3'b000; end else if (count < 4) begin count <= count+1'b1; end else begin count <= 3'b000; Q <= ~Q; end end endmodule
divide_by_50.v
module divide_by_50(Q,CLK,RST); input CLK, RST; output Q; reg Q; reg [4:0] count; always @ (posedge CLK or negedge RST) begin if (~RST) begin Q <= 1'b0; count <= 5'b00000; end else if (count < 24) begin count <= count+1'b1; end else begin count <= 5'b00000; Q <= ~Q; end end endmodule
hex_7seg.v
module hex_7seg(hex_digit,seg); input [3:0] hex_digit; output [6:0] seg; reg [6:0] seg; // seg = {g,f,e,d,c,b,a}; // 0 is on and 1 is off always @ (hex_digit) case (hex_digit) 4'h0: seg = 7'b1000000; 4'h1: seg = 7'b1111001; // ---a---- 4'h2: seg = 7'b0100100; // | | 4'h3: seg = 7'b0110000; // f b 4'h4: seg = 7'b0011001; // | | 4'h5: seg = 7'b0010010; // ---g---- 4'h6: seg = 7'b0000010; // | | 4'h7: seg = 7'b1111000; // e c 4'h8: seg = 7'b0000000; // | | 4'h9: seg = 7'b0011000; // ---d---- 4'ha: seg = 7'b0001000; 4'hb: seg = 7'b0000011; 4'hc: seg = 7'b1000110; 4'hd: seg = 7'b0100001; 4'he: seg = 7'b0000110; 4'hf: seg = 7'b0001110; endcase endmodule
oneshot.v
module oneshot(output reg pulse_out, input trigger_in, input clk); reg delay; always @ (posedge clk) begin if (trigger_in && !delay) pulse_out <= 1'b1; else pulse_out <= 1'b0; delay <= trigger_in; end endmodule
fit.summary
Fitter Status : Successful - Mon Jan 21 14:50:15 2008 Quartus II Version : 7.2 Build 175 11/20/2007 SP 1 SJ Web Edition Revision Name : diglab3 Top-level Entity Name : diglab3 Family : Cyclone II Device : EP2C35F672C6 Timing Models : Final Total logic elements : 75 / 33,216 ( < 1 % ) Total combinational functions : 74 / 33,216 ( < 1 % ) Dedicated logic registers : 44 / 33,216 ( < 1 % ) Total registers : 44 Total pins : 178 / 475 ( 37 % ) Total virtual pins : 0 Total memory bits : 0 / 483,840 ( 0 % ) Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % ) Total PLLs : 0 / 4 ( 0 % )
tan.summary
-------------------------------------------------------------------------------------- Timing Analyzer Summary -------------------------------------------------------------------------------------- Type : Worst-case tco Slack : N/A Required Time : None Actual Time : 24.611 ns From : decimal_counter:count3|A[1] To : HEX3[6] From Clock : CLOCK_50 To Clock : -- Failed Paths : 0 Type : Worst-case tpd Slack : N/A Required Time : None Actual Time : 9.857 ns From : SW[16] To : LEDR[16] From Clock : -- To Clock : -- Failed Paths : 0 Type : Clock Setup: 'KEY[3]' Slack : N/A Required Time : None Actual Time : 306.18 MHz ( period = 3.266 ns ) From : decimal_counter:count2|A[3] To : decimal_counter:count2|OVERFLOW From Clock : KEY[3] To Clock : KEY[3] Failed Paths : 0 Type : Clock Setup: 'CLOCK_50' Slack : N/A Required Time : None Actual Time : 306.18 MHz ( period = 3.266 ns ) From : decimal_counter:count2|A[3] To : decimal_counter:count2|OVERFLOW From Clock : CLOCK_50 To Clock : CLOCK_50 Failed Paths : 0 Type : Total number of failed paths Slack : Required Time : Actual Time : From : To : From Clock : To Clock : Failed Paths : 0 --------------------------------------------------------------------------------------
Maintained by John Loomis, last updated Mon Jan 21 14:51:57 2008