Altera DE2 Project lcdlab2

Download: design files

This lab combines the timer project (diglab3) with the lcd display project (lcdlab1)

Contents

Top-Level Module

The following excerpt shows how to map the decinal counter output to ASCII charcters for the LCD display.

parameter LINE1 = 5;
parameter LUT_SIZE = LINE1+5;

always
begin
    case(LUT_INDEX)
    0:    LUT_DATA    <=    9'h038;
    1:    LUT_DATA    <=    9'h00C;
    2:    LUT_DATA    <=    9'h001;
    3:    LUT_DATA    <=    9'h006;
    4:    LUT_DATA    <=    9'h080;
    //    Line 1
    LINE1+0:    LUT_DATA    <=    9'h120;    // blanks    
    LINE1+1:    LUT_DATA    <=    9'h120;
    LINE1+2:    LUT_DATA    <=    {5'h13,digit3};
    LINE1+3:    LUT_DATA    <=    {5'h13,digit2};
    LINE1+4:    LUT_DATA    <=    {5'h13,digit1};
    LINE1+5:    LUT_DATA    <=    {5'h13,digit0};
    default:        
        LUT_DATA    <=    9'dx ;
    endcase
end

The LCD display state machine is restarted once per second, corresponding to the timer update rate.

Reference

Verilog source and Quartus compilation report


Maintained by John Loomis, last updated 23 January 2008