de2risc1.vmodule de2risc1( input CLOCK_50, // 50 MHz clock input [3:0] KEY, // Pushbutton[3:0] input [17:0] SW, // Toggle Switch[17:0] output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7, // Seven Segment Digits output [8:0] LEDG, // LED Green output [17:0] LEDR, // LED Red inout [35:0] GPIO_0,GPIO_1, // GPIO Connections // LCD Module 16X2 output LCD_ON, // LCD Power ON/OFF output LCD_BLON, // LCD Back Light ON/OFF output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read output LCD_EN, // LCD Enable output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data inout [7:0] LCD_DATA // LCD Data bus 8 bits ); // All inout port turn to tri-state assign GPIO_0 = 36'hzzzzzzzzz; assign GPIO_1 = 36'hzzzzzzzzz; wire RST; assign RST = KEY[0]; // reset delay gives some time for peripherals to initialize wire DLY_RST; Reset_Delay r0( .iCLK(CLOCK_50),.oRESET(DLY_RST) ); wire reset = RST & DLY_RST; // Send switches to red leds assign LEDR = SW; // turn off green leds assign LEDG = 0; // turn LCD ON assign LCD_ON = 1'b1; assign LCD_BLON = 1'b1; wire [6:0] myclock; clock_divider c1( .CLK(CLOCK_50), .RST(reset), .clock(myclock) ); // target processor clock wire mClock; // clock manually or at 1 Hz assign mClock = (SW[0]? myclock[0]: ~KEY[3]); wire [7:0] PC; wire [31:0] IR; srisc1 u1( .clock(mClock), .reset(reset), .pc(PC), .ir(IR) ); wire [4:0] indx; wire [7:0] chr; LCD_string u2( .index(indx), .out(chr), .pc(PC), .ir(IR) ); LCD_Display u3( // Host Side .index(indx), .character(chr), .iCLK_50MHZ(CLOCK_50), .iRST_N(reset), // LCD Side .DATA_BUS(LCD_DATA), .LCD_RW(LCD_RW), .LCD_E(LCD_EN), .LCD_RS(LCD_RS) ); // blank unused 7-segment digits assign HEX0 = 7'b111_1111; assign HEX1 = 7'b111_1111; assign HEX2 = 7'b111_1111; assign HEX3 = 7'b111_1111; assign HEX4 = 7'b111_1111; assign HEX5 = 7'b111_1111; assign HEX6 = 7'b111_1111; assign HEX7 = 7'b111_1111; endmodule
clock_divider.v
module clock_divider(input CLK, input RST, output [6:0] clock);
wire clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz;
assign clock = {clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz};
divide_by_50 d6(clk_1Mhz,CLK,RST);
divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);
divide_by_10 d4(clk_10Khz,clk_100Khz,RST);
divide_by_10 d3(clk_1Khz,clk_10Khz,RST);
divide_by_10 d2(clk_100hz,clk_1Khz,RST);
divide_by_10 d1(clk_10hz,clk_100hz,RST);
divide_by_10 d0(clk_1hz,clk_10hz,RST);
endmodule
divide_by_10.v
module divide_by_10(Q,CLK,RST);
input CLK, RST;
output Q;
reg Q;
reg [2:0] count;
always @ (posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 3'b000;
end
else if (count < 4)
begin
count <= count+1'b1;
end
else
begin
count <= 3'b000;
Q <= ~Q;
end
end
endmodule
divide_by_50.v
module divide_by_50(Q,CLK,RST);
input CLK, RST;
output Q;
reg Q;
reg [4:0] count;
always @ (posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 5'b00000;
end
else if (count < 24)
begin
count <= count+1'b1;
end
else
begin
count <= 5'b00000;
Q <= ~Q;
end
end
endmodule
inst.v
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: inst.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 175 11/20/2007 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module inst (
address,
clock,
q);
input [7:0] address;
input clock;
output [31:0] q;
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "isa1.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "isa1.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "isa1.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
LCD_Display.v
/*
SW8 (GLOBAL RESET) resets LCD
ENTITY LCD_Display IS
-- Enter number of live Hex hardware data values to display
-- (do not count ASCII character constants)
GENERIC(Num_Hex_Digits: Integer:= 2);
-----------------------------------------------------------------------
-- LCD Displays 16 Characters on 2 lines
-- LCD_display string is an ASCII character string entered in hex for
-- the two lines of the LCD Display (See ASCII to hex table below)
-- Edit LCD_Display_String entries above to modify display
-- Enter the ASCII character's 2 hex digit equivalent value
-- (see table below for ASCII hex values)
-- To display character assign ASCII value to LCD_display_string(x)
-- To skip a character use 8'h20" (ASCII space)
-- To dislay "live" hex values from hardware on LCD use the following:
-- make array element for that character location 8'h0" & 4-bit field from Hex_Display_Data
-- state machine sees 8'h0" in high 4-bits & grabs the next lower 4-bits from Hex_Display_Data input
-- and performs 4-bit binary to ASCII conversion needed to print a hex digit
-- Num_Hex_Digits must be set to the count of hex data characters (ie. "00"s) in the display
-- Connect hardware bits to display to Hex_Display_Data input
-- To display less than 32 characters, terminate string with an entry of 8'hFE"
-- (fewer characters may slightly increase the LCD's data update rate)
-------------------------------------------------------------------
-- ASCII HEX TABLE
-- Hex Low Hex Digit
-- Value 0 1 2 3 4 5 6 7 8 9 A B C D E F
------\----------------------------------------------------------------
--H 2 | SP ! " # $ % & ' ( ) * + , - . /
--i 3 | 0 1 2 3 4 5 6 7 8 9 : ; < = > ?
--g 4 | @ A B C D E F G H I J K L M N O
--h 5 | P Q R S T U V W X Y Z [ \ ] ^ _
-- 6 | ` a b c d e f g h i j k l m n o
-- 7 | p q r s t u v w x y z { | } ~ DEL
-----------------------------------------------------------------------
-- Example "A" is row 4 column 1, so hex value is 8'h41"
-- *see LCD Controller's Datasheet for other graphics characters available
*/
module LCD_Display(
output reg [4:0] index,
input [7:0] character,
input iCLK_50MHZ,
input iRST_N,
output reg LCD_RS,
output reg LCD_E,
output LCD_RW,
inout [7:0] DATA_BUS);
parameter
HOLD = 4'h0,
FUNC_SET = 4'h1,
DISPLAY_ON = 4'h2,
MODE_SET = 4'h3,
Print_String = 4'h4,
LINE2 = 4'h5,
RETURN_HOME = 4'h6,
DROP_LCD_E = 4'h7,
RESET1 = 4'h8,
RESET2 = 4'h9,
RESET3 = 4'ha,
DISPLAY_OFF = 4'hb,
DISPLAY_CLEAR = 4'hc;
reg [3:0] state, next_command;
// Enter new ASCII hex data above for LCD Display
reg [7:0] DATA_BUS_VALUE;
reg [19:0] CLK_COUNT_400HZ;
reg CLK_400HZ, LCD_RW_INT;
// BIDIRECTIONAL TRI STATE LCD DATA BUS
assign DATA_BUS = (LCD_RW_INT? 8'bZZZZZZZZ: DATA_BUS_VALUE);
assign LCD_RW = LCD_RW_INT;
always @(posedge iCLK_50MHZ or negedge iRST_N)
if (!iRST_N)
begin
CLK_COUNT_400HZ <= 20'h00000;
CLK_400HZ <= 1'b0;
end
else if (CLK_COUNT_400HZ < 20'h0F424)
begin
CLK_COUNT_400HZ <= CLK_COUNT_400HZ + 1'b1;
end
else
begin
CLK_COUNT_400HZ <= 20'h00000;
CLK_400HZ <= ~CLK_400HZ;
end
// State Machine to send commands and data to LCD DISPLAY
always @(posedge CLK_400HZ or negedge iRST_N)
if (!iRST_N)
begin
state <= RESET1;
end
else
case (state)
RESET1:
// Set Function to 8-bit transfer and 2 line display with 5x8 Font size
// see Hitachi HD44780 family data sheet for LCD command and timing details
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= RESET2;
index <= 5'b00000;
end
RESET2:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= RESET3;
end
RESET3:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= FUNC_SET;
end
// EXTRA STATES ABOVE ARE NEEDED FOR RELIABLE PUSHBUTTON RESET OF LCD
FUNC_SET:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h38;
state <= DROP_LCD_E;
next_command <= DISPLAY_OFF;
end
// Turn off Display and Turn off cursor
DISPLAY_OFF:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h08;
state <= DROP_LCD_E;
next_command <= DISPLAY_CLEAR;
end
// Clear Display and Turn off cursor
DISPLAY_CLEAR:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h01;
state <= DROP_LCD_E;
next_command <= DISPLAY_ON;
end
// Turn on Display and Turn off cursor
DISPLAY_ON:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h0C;
state <= DROP_LCD_E;
next_command <= MODE_SET;
end
// Set write mode to auto increment address and move cursor to the right
MODE_SET:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h06;
state <= DROP_LCD_E;
next_command <= Print_String;
end
// Write ASCII hex character in first LCD character location
Print_String:
begin
state <= DROP_LCD_E;
LCD_E <= 1'b1;
LCD_RS <= 1'b1;
LCD_RW_INT <= 1'b0;
// ASCII character to output
if (character[7:4] != 4'h0)
DATA_BUS_VALUE <= character;
// Convert 4-bit value to an ASCII hex digit
else if (character[3:0] >9)
// ASCII A...F
DATA_BUS_VALUE <= {4'h4,character[3:0]-4'h9};
else
// ASCII 0...9
DATA_BUS_VALUE <= {4'h3,character[3:0]};
// Loop to send out 32 characters to LCD Display (16 by 2 lines)
if ((index < 31) && (character != 8'hFE))
index <= index + 1'b1;
else
index <= 5'b00000;
// Jump to second line?
if (index == 15)
next_command <= LINE2;
// Return to first line?
else if ((index == 31) || (character == 8'hFE))
next_command <= RETURN_HOME;
else
next_command <= Print_String;
end
// Set write address to line 2 character 1
LINE2:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'hC0;
state <= DROP_LCD_E;
next_command <= Print_String;
end
// Return write address to first character postion on line 1
RETURN_HOME:
begin
LCD_E <= 1'b1;
LCD_RS <= 1'b0;
LCD_RW_INT <= 1'b0;
DATA_BUS_VALUE <= 8'h80;
state <= DROP_LCD_E;
next_command <= Print_String;
end
// The next three states occur at the end of each command or data transfer to the LCD
// Drop LCD E line - falling edge loads inst/data to LCD controller
DROP_LCD_E:
begin
LCD_E <= 1'b0;
state <= HOLD;
end
// Hold LCD inst/data valid after falling edge of E line
HOLD:
begin
state <= next_command;
end
endcase
endmodule
LCD_string.v
/*
SW8 (GLOBAL RESET) resets LCD
ENTITY LCD_Display IS
-- Enter number of live Hex hardware data values to display
-- (do not count ASCII character constants)
GENERIC(Num_Hex_Digits: Integer:= 2);
-----------------------------------------------------------------------
-- LCD Displays 16 Characters on 2 lines
-- LCD_display string is an ASCII character string entered in hex for
-- the two lines of the LCD Display (See ASCII to hex table below)
-- Edit LCD_Display_String entries above to modify display
-- Enter the ASCII character's 2 hex digit equivalent value
-- (see table below for ASCII hex values)
-- To display character assign ASCII value to LCD_display_string(x)
-- To skip a character use 8'h20" (ASCII space)
-- To dislay "live" hex values from hardware on LCD use the following:
-- make array element for that character location 8'h0" & 4-bit field from Hex_Display_Data
-- state machine sees 8'h0" in high 4-bits & grabs the next lower 4-bits from Hex_Display_Data input
-- and performs 4-bit binary to ASCII conversion needed to print a hex digit
-- Num_Hex_Digits must be set to the count of hex data characters (ie. "00"s) in the display
-- Connect hardware bits to display to Hex_Display_Data input
-- To display less than 32 characters, terminate string with an entry of 8'hFE"
-- (fewer characters may slightly increase the LCD's data update rate)
-------------------------------------------------------------------
-- ASCII HEX TABLE
-- Hex Low Hex Digit
-- Value 0 1 2 3 4 5 6 7 8 9 A B C D E F
------\----------------------------------------------------------------
--H 2 | SP ! " # $ % & ' ( ) * + , - . /
--i 3 | 0 1 2 3 4 5 6 7 8 9 : ; < = > ?
--g 4 | @ A B C D E F G H I J K L M N O
--h 5 | P Q R S T U V W X Y Z [ \ ] ^ _
-- 6 | ` a b c d e f g h i j k l m n o
-- 7 | p q r s t u v w x y z { | } ~ DEL
-----------------------------------------------------------------------
-- Example "A" is row 4 column 1, so hex value is 8'h41"
-- *see LCD Controller's Datasheet for other graphics characters available
*/
module LCD_string(input [4:0] index, output reg [7:0] out, input [7:0] pc, input [31:0] ir);
// ASCII hex values for LCD Display
// Enter Live Hex Data Values from hardware here
// LCD DISPLAYS THE FOLLOWING:
//----------------------------
//| PC xx |
//| IR xxxxxxxx |
//----------------------------
// Line 1
always
case (index)
5'h00: out <= 8'h50; // P
5'h01: out <= 8'h43; // C
5'h02: out <= 8'h20;
5'h03: out <= {4'h0,pc[7:4]};
5'h04: out <= {4'h0,pc[3:0]};
// Line 2
5'h10: out <= 8'h49; // I
5'h11: out <= 8'h52; // R
5'h12: out <= 8'h20;
5'h13: out <= {4'h0,ir[31:28]};
5'h14: out <= {4'h0,ir[27:24]};
5'h15: out <= {4'h0,ir[23:20]};
5'h16: out <= {4'h0,ir[19:16]};
5'h17: out <= {4'h0,ir[15:12]};
5'h18: out <= {4'h0,ir[11:8]};
5'h19: out <= {4'h0,ir[7:4]};
5'h1a: out <= {4'h0,ir[3:0]};
default: out <= 8'h20;
endcase
endmodule
reset_delay.v
module Reset_Delay(iCLK,oRESET);
input iCLK;
output reg oRESET;
reg [19:0] Cont;
always@(posedge iCLK)
begin
if(Cont!=20'hFFFFF)
begin
Cont <= Cont+1'b1;
oRESET <= 1'b0;
end
else
oRESET <= 1'b1;
end
endmodule
srisc1.v
module srisc1(input clock, input reset, output reg [7:0] pc, output [31:0] ir);
wire [31:0] da, db, dc;
wire [4:0] ra, rb, rc;
wire write_enable;
// instantiate memory
inst inst_cache(
.address(pc),
.clock(clock),
.q(ir)
);
always @(posedge clock or negedge reset)
begin
if (!reset) pc <= 8'h00;
else pc <= pc + 8'h01;
end
endmodule
fit.summary
Fitter Status : Successful - Tue Feb 12 21:12:17 2008
Quartus II Version : 7.2 Build 175 11/20/2007 SP 1 SJ Web Edition
Revision Name : de2risc1
Top-level Entity Name : de2risc1
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Final
Total logic elements : 214 / 33,216 ( < 1 % )
Total combinational functions : 214 / 33,216 ( < 1 % )
Dedicated logic registers : 118 / 33,216 ( < 1 % )
Total registers : 118
Total pins : 191 / 475 ( 40 % )
Total virtual pins : 0
Total memory bits : 8,192 / 483,840 ( 2 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )
tan.summary-------------------------------------------------------------------------------------- Timing Analyzer Summary -------------------------------------------------------------------------------------- Type : Worst-case tsu Slack : N/A Required Time : None Actual Time : -5.141 ns From : KEY[0] To : LCD_Display:u3|next_command.RESET3 From Clock : -- To Clock : CLOCK_50 Failed Paths : 0 Type : Worst-case tco Slack : N/A Required Time : None Actual Time : 20.455 ns From : LCD_Display:u3|DATA_BUS_VALUE[3] To : LCD_DATA[3] From Clock : CLOCK_50 To Clock : -- Failed Paths : 0 Type : Worst-case tpd Slack : N/A Required Time : None Actual Time : 9.857 ns From : SW[16] To : LEDR[16] From Clock : -- To Clock : -- Failed Paths : 0 Type : Worst-case th Slack : N/A Required Time : None Actual Time : 6.181 ns From : KEY[0] To : LCD_Display:u3|LCD_RS From Clock : -- To Clock : CLOCK_50 Failed Paths : 0 Type : Clock Setup: 'CLOCK_50' Slack : N/A Required Time : None Actual Time : 89.20 MHz ( period = 11.211 ns ) From : srisc1:u1|inst:inst_cache|altsyncram:altsyncram_component|altsyncram_6j71:auto_generated|ram_block1a0~porta_address_reg7 To : LCD_Display:u3|DATA_BUS_VALUE[1] From Clock : CLOCK_50 To Clock : CLOCK_50 Failed Paths : 0 Type : Clock Setup: 'SW[0]' Slack : N/A Required Time : None Actual Time : Restricted to 260.01 MHz ( period = 3.846 ns ) From : srisc1:u1|pc[5] To : srisc1:u1|inst:inst_cache|altsyncram:altsyncram_component|altsyncram_6j71:auto_generated|ram_block1a0~porta_address_reg5 From Clock : SW[0] To Clock : SW[0] Failed Paths : 0 Type : Clock Setup: 'KEY[3]' Slack : N/A Required Time : None Actual Time : Restricted to 260.01 MHz ( period = 3.846 ns ) From : srisc1:u1|pc[5] To : srisc1:u1|inst:inst_cache|altsyncram:altsyncram_component|altsyncram_6j71:auto_generated|ram_block1a0~porta_address_reg5 From Clock : KEY[3] To Clock : KEY[3] Failed Paths : 0 Type : Clock Hold: 'CLOCK_50' Slack : Not operational: Clock Skew > Data Delay Required Time : None Actual Time : N/A From : Reset_Delay:r0|oRESET To : LCD_Display:u3|next_command.RETURN_HOME From Clock : CLOCK_50 To Clock : CLOCK_50 Failed Paths : 27 Type : Total number of failed paths Slack : Required Time : Actual Time : From : To : From Clock : To Clock : Failed Paths : 27 --------------------------------------------------------------------------------------
Maintained by John Loomis, last updated Tue Feb 12 21:19:51 2008