Bits	Field	Description
31:3		Reserved
2	EH	EH is the exception handler bit. The processor sets EH to one when an exception occurs (including breaks). Software clears EH to zero when ready to handle exceptions again. EH is used by the MMU to determine whether a TLB miss exception is a fast TLB miss or a double TLB miss. In systems without an MMU, EH is always zero.
1	U	U is the user mode bit. When U = 1, the processor operates in user mode. When U = 0, the processor operates in supervisor mode. In systems without an MMU, U is always zero.
0	PIE	PIE is the processor interrupt-enable bit. When PIE = 0, interrupts are ignored. When PIE = 1, interrupts can be taken, depending on the value of the ienable register.

The ienable register controls the handling of external hardware interrupts. Each bit of the ienable register corresponds to one of the interrupt inputs, irq0 through irq31. A value of one in bit n means that the corresponding irqn interrupt is enabled; a bit value of zero means that the corresponding interrupt is disabled. See “Exception Processing” on page 3–34 for more information.

The value of the ipending register indicates the value of the interrupt signals driven into the processor. A value of one in bit n means that the corresponding irqn input is asserted. Writing a value to the ipending register has no effect.

The cpuid register holds a constant value that uniquely identifies each processor in a multi-processor system. The cpuid value is determined at system generation time and is guaranteed to be unique for each processor in the system. Writing to the cpuid register has no effect.

When the extra exception information option is enabled, the Nios II processor provides information useful to system software for exception processing in the exception and badaddr registers when an exception occurs. When your system contains an MMU or MPU, the extra exception information is always enabled. When no MMU or MPU is present, the Nios II Megawizard interface gives you the option to have the processor provide the extra exception information.

To see how to control the extra exception information option, refer to the Instantiating the Nios II Processor in SOPC Builder chapter of the Nios II Processor Reference Handbook.

The table below shows the layout of the exception register.

Bits	Field	Description
31:7	Reserved
6:2	CAUSE	CAUSE contains a code for the highestpriority exception occurring at the time.
1:0	Reserved

The pteaddr register contains the virtual address of the operating system’s page table and is only available in systems with an MMU. The pteaddr register layout accelerates fast TLB miss exception handling. The table below shows the layout of the pteaddr register.

Bits	Field	Description
31:22	PTBASE	base virtual address of the page table.
21:2	VPN	virtual page number. VPN can be set by both hardware and software.
1:0	Reserved

Software writes to the PTBASE field when switching processes. Hardware never writes to the PTBASE field.

Software writes to the VPN field when writing a TLB entry. Hardware writes to the VPN field on a fast TLB miss exception, a TLB permission violation exception, or on a TLB read operation. The VPN field is not written on any exceptions taken when an exception is already active, that is, when status.EH is already one.

The tlbacc register is used to access TLB entries and is only available in systems with an MMU. The tlbacc register holds values that software will write into a TLB entry or has previously read from a TLB entry. The tlbacc register provides access to only a portion of a complete TLB entry. pteaddr.VPN and tlbmisc.PID hold the remaining TLB entry fields.

The tlbmisc register contains the remaining TLB-related fields and is only available in systems with an MMU. Table 3–17 shows the layout of the tlbmisc register.

When the extra exception information option is enabled, the Nios II processor provides information useful to system software for exception processing in the exception and badaddr registers when an exception occurs. When your system contains an MMU or MPU, the extra exception information is always enabled. When no MMU or MPU is present, the Nios II Megawizard interface gives you the option to have the processor provide the extra exception information.

To see how to control the extra exception information option, refer to the Instantiating the Nios II Processor in SOPC Builder chapter of the Nios II Processor Reference Handbook.

When the option for extra exception information is enabled and a processor exception occurs, the badaddr register contains the byte instruction or data address associated with certain exceptions at the time the exception occurred. Table 3–31 on page 3–35 shows which exceptions write the badaddr register along with the value written. Table 3–19 shows the layout of the badaddr register.

The config register configures Nios II runtime behaviors that do not need to be preserved during exception processing (in contrast to the information in the status register). Table 3–21 shows the layout of the config register.

The mpubase register works in conjunction with the mpuacc register to set and retrieve MPU region information and is only available in systems with an MPU. Table 3–23 shows the layout of the mpubase register.

The mpuacc register works in conjunction with the mpubase register to set and retrieve MPU region information and is only available in systems with an MPU. The mpuacc register consists of attributes that will be set or have been retrieved which define the MPU region. The mpuacc register only holds a portion of the attributes that define an MPU region. The remaining portion of the MPU region definition is held by the BASE field of the mpubase register.