Project: div10

div10.v

module div10(input [15:0] num, output [19:0] bcd);

wire [15:0] s1, s2, s3, s4;
wire [3:0] ten = 4'd10;
ip_divide u1(.denom(ten),.numer(num),.quotient(s1),.remain(bcd[3:0]));
ip_divide u2(.denom(ten),.numer(s1),.quotient(s2),.remain(bcd[7:4]));
ip_divide u3(.denom(ten),.numer(s2),.quotient(s3),.remain(bcd[11:8]));
ip_divide u4(.denom(ten),.numer(s3),.quotient(s4),.remain(bcd[15:12]));
assign bcd[19:16] = s4[3:0];
endmodule

Quartus Compilation Summary

fit.summary

Fitter Status : Successful - Mon Oct 17 21:03:26 2011
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : div10
Top-level Entity Name : div10
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Final
Total logic elements : 202 / 33,216 ( < 1 % )
    Total combinational functions : 202 / 33,216 ( < 1 % )
    Dedicated logic registers : 0 / 33,216 ( 0 % )
Total registers : 0
Total pins : 36 / 475 ( 8 % )
Total virtual pins : 0
Total memory bits : 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )

tan.summary

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Timing Analyzer Summary
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Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 31.069 ns
From           : num[13]
To             : bcd[11]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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