Project: div10

Contents

Verilog Files

Quartus Files

Verilog Files

Quartus Compilation Summary

Fitter Status : Successful - Mon Oct 17 10:36:46 2011
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : div10
Top-level Entity Name : ip_divide
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Final
Total logic elements : 144 / 33,216 ( < 1 % )
    Total combinational functions : 144 / 33,216 ( < 1 % )
    Dedicated logic registers : 0 / 33,216 ( 0 % )
Total registers : 0
Total pins : 40 / 475 ( 8 % )
Total virtual pins : 0
Total memory bits : 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )

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Timing Analyzer Summary
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Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 42.981 ns
From           : denom[3]
To             : remain[2]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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Maintained by John Loomis, last updated Mon Oct 17 10:37:36 2011