Chapter 3 – Memory Logic

Clocked Inverter and Dyanamic Latch (SPICE)

Download LTspice files from spice_clocked_inverter.zip.

Static Latches

Download Verilog files from latch.zip.

Flip-Flops

Download Verilog project files from memtest.zip

• version 1 evaluate master_slave module (Quartus documentation)
• version 2 evaluate flipflop module

DE2 Project to compare latch and flip-flop operation

SW[17] (left-most) controls enable signal. SW[0] (right-most) controls D signal.

Download Verilog project files from memtlab1.zip

• version 1 latch alone (Quartus documentation)
• version 2 latch vs. flipflop

Registers

Download Verilog project files from register.zip.

• Quartus II documentation

ramtest

Download Verilog project files from ramtest.zip.

• Quartus project documentation
• Quartus simulation table

DE2 Project to test RAM operation

SW[17] (left-most) controls clock: switch on for manual control (using KEY[3]), switch off to use 1 sec clock. KEY[3] is reset switch. The seven-segment displays read the following values (in hex)

7-seg	display
HEX7:6	addr
HEX5:4	q
HEX3:2	qa
HEX1:0	inst

Download Verilog project files from memtlab2.zip

• memlab2 (Quartus documentation)

Maintained by John Loomis, last updated 3 Nov 2011