Project: memlab1

memlab1.v

module memlab1(
  // Clock Input (50 MHz)
  input  CLOCK_50,
  //  Push Buttons
  input  [3:0]  KEY,
  //  DPDT Switches 
  input  [17:0]  SW,
  //  7-SEG Displays
  output  [6:0]  HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
  //  LEDs
  output  [8:0]  LEDG,  //  LED Green[8:0]
  output  [17:0]  LEDR //  LED Red[17:0]
);

// Connect dip switches to red LEDs
assign LEDR[17:0] = SW[17:0];

// turn off green LEDs
assign LEDG[8:0] = 0;

// instantiate and connect memory

wire D,S,Q1,Q2;
assign D = SW[0];
assign S = SW[17];
latch2 u1(D,S,Q1);
flipflop u2(Q2,D,S);

// map to 7-segment displays

hex_7seg dsp0({3'h0,Q1},HEX0);
hex_7seg dsp1({3'h0,Q2},HEX1);


localparam blank = ~7'h00; 

// blank remaining digits
assign HEX2 = blank;
assign HEX3 = blank;
assign HEX4 = blank;
assign HEX5 = blank;
assign HEX6 = blank;
assign HEX7 = blank;

endmodule

latch2.v

module latch2(input D,S, output Q);


assign Q = (S? D: Q);


endmodule

hex_7seg.v

module hex_7seg(
input [3:0] hex_digit,
output reg [6:0] seg
);
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off

always @ (hex_digit)
case (hex_digit)
        4'h0: seg = ~7'h3F;
        4'h1: seg = ~7'h06;     // ---a----
        4'h2: seg = ~7'h5B;     // |      |
        4'h3: seg = ~7'h4F;     // f      b
        4'h4: seg = ~7'h66;     // |      |
        4'h5: seg = ~7'h6D;     // ---g----
        4'h6: seg = ~7'h7D;     // |      |
        4'h7: seg = ~7'h07;     // e      c
        4'h8: seg = ~7'h7F;     // |      |
        4'h9: seg = ~7'h67;     // ---d----
        4'ha: seg = ~7'h77;
        4'hb: seg = ~7'h7C;
        4'hc: seg = ~7'h39;
        4'hd: seg = ~7'h5E;
        4'he: seg = ~7'h79;
        4'hf: seg = ~7'h71;
endcase

endmodule

flipflop.v

module flipflop(output reg Q, input D, CLK);
    always @ (negedge CLK)
        Q = D;
endmodule

Quartus Compilation Summary

fit.summary

Fitter Status : Successful - Wed Oct 26 12:17:04 2011
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : memlab1
Top-level Entity Name : memlab1
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Final
Total logic elements : 2 / 33,216 ( < 1 % )
    Total combinational functions : 1 / 33,216 ( < 1 % )
    Dedicated logic registers : 1 / 33,216 ( < 1 % )
Total registers : 1
Total pins : 106 / 475 ( 22 % )
Total virtual pins : 0
Total memory bits : 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )

tan.summary

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 1.166 ns
From           : SW[0]
To             : latch2:u1|Q
From Clock     : --
To Clock       : SW[17]
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.895 ns
From           : flipflop:u2|Q
To             : HEX1[0]
From Clock     : SW[17]
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 9.837 ns
From           : SW[17]
To             : LEDR[17]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.200 ns
From           : SW[0]
To             : flipflop:u2|Q
From Clock     : --
To Clock       : SW[17]
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------