Project: memtest

memtest.v

module memtest(output Q, input D, S);

flipflop u1(Q,D,S);

endmodule

latch2.v

module latch2(input D,S, output Q);


assign Q = (S? D: Q);


endmodule

master_slave.v

module master_slave(output Q, input D, clk);
    wire w;
    latch2 master(D,clk,w);
    latch2 slave(w,~clk,Q);
endmodule

flipflop.v

module flipflop(output reg Q, input D, CLK);
    always @ (negedge CLK)
        Q = D;
endmodule

Quartus Compilation Summary

fit.summary

Fitter Status : Successful - Wed Oct 26 10:42:48 2011
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : memtest
Top-level Entity Name : memtest
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Final
Total logic elements : 1 / 33,216 ( < 1 % )
    Total combinational functions : 0 / 33,216 ( 0 % )
    Dedicated logic registers : 1 / 33,216 ( < 1 % )
Total registers : 1
Total pins : 3 / 475 ( < 1 % )
Total virtual pins : 0
Total memory bits : 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )

tan.summary

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -0.322 ns
From           : D
To             : flipflop:u1|Q
From Clock     : --
To Clock       : S
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 5.807 ns
From           : flipflop:u1|Q
To             : Q
From Clock     : S
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.552 ns
From           : D
To             : flipflop:u1|Q
From Clock     : --
To Clock       : S
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------