Project: register

register.v

// Simple register
module register
#(parameter WIDTH=4)(
output reg [WIDTH-1:0] Q,
input [WIDTH-1:0] D,
input clk, load, clr
);
   
    always @(posedge clk or negedge clr)
    begin
    if (~clr) Q <= 0;
    else if (load) Q <= D;
    end

endmodule

Quartus Compilation Summary

fit.summary

Fitter Status : Successful - Thu Oct 27 10:01:49 2011
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : register
Top-level Entity Name : register
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Final
Total logic elements : 4 / 33,216 ( < 1 % )
    Total combinational functions : 0 / 33,216 ( 0 % )
    Dedicated logic registers : 4 / 33,216 ( < 1 % )
Total registers : 4
Total pins : 11 / 475 ( 2 % )
Total virtual pins : 0
Total memory bits : 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )

tan.summary

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.992 ns
From           : D[1]
To             : Q[1]~reg0
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.241 ns
From           : Q[3]~reg0
To             : Q[3]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.116 ns
From           : D[0]
To             : Q[0]~reg0
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------