Project: ramtest

ramtest.v

module ramtest 
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6)
(
    input clk, reset_n,
    output [(ADDR_WIDTH-1):0] addr,
    output we,
    output  [(DATA_WIDTH-1):0] q, qa,
    output reg [7:0] pc,
    output reg [(DATA_WIDTH-1):0] inst
);

defparam dev1.DATA_WIDTH = DATA_WIDTH, dev1.ADDR_WIDTH=ADDR_WIDTH;

single_port_ram dev1
(
    .data(qa),
    .addr(addr),
    .we(we),
    .clk(clk),
    .q(q)
);
wire [ADDR_WIDTH-1:0] nextpc = pc + 1'b1;
assign addr = state==IF? q[ADDR_WIDTH-1:0]: nextpc;

assign we = state==EX? q[7:6]==2'b01: );
assign qa = state==EX? q: 8'h00;


reg [1:0] state;
localparam HALT = 3, IF = 0, EX=1;

always @(posedge clk or negedge reset_n)
begin
    if (!reset_n)
    begin
        pc <= 6'h3F;
        state = IF;
    end
    else
    case (state)
    IF:
    begin
    pc <= nextpc;
    state <= EX;
    end
    EX:
    begin
    if (q==0) state <= HALT;
    else
        state <= IF;
    end
    HALT:
    begin
        pc <= 6'h3F;
        state <= HALT;
    end
    default:
        state <= HALT;
    endcase
end

endmodule

single_port_ram.v

// Quartus II Verilog Template
// Single port RAM with single read/write address 

module single_port_ram 
#(parameter DATA_WIDTH=16, parameter ADDR_WIDTH=7)
(
    input [(DATA_WIDTH-1):0] data,
    input [(ADDR_WIDTH-1):0] addr,
    input we, clk,
    output [(DATA_WIDTH-1):0] q
);

    // Declare the RAM variable
    reg [DATA_WIDTH-1:0] ram[0:2**ADDR_WIDTH-1];
    
    // Initialize the RAM with $readmemb.  Put the memory contents
    // in the file single_port_rom_init.txt.  Without this file,
    // this design will not compile.
    // See Verilog LRM 1364-2001 Section 17.2.8 for details on the
    // format of this file.

    initial
    begin
        $readmemh("ram_init.txt", ram);
    end

    // Variable to hold the registered read address
    reg [ADDR_WIDTH-1:0] addr_reg;

    always @ (posedge clk)
    begin
        // Write
        if (we)
            ram[addr] <= data;

        addr_reg <= addr;
    end

    // Continuous assignment implies read returns NEW data.
    // This is the natural behavior of the TriMatrix memory
    // blocks in Single Port mode.  
    assign q = ram[addr_reg];

endmodule

Quartus Compilation Summary

fit.summary

Fitter Status : Successful - Sun Oct 30 18:16:20 2011
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : ramtest
Top-level Entity Name : ramtest
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Final
Total logic elements : 29 / 33,216 ( < 1 % )
    Total combinational functions : 29 / 33,216 ( < 1 % )
    Dedicated logic registers : 9 / 33,216 ( < 1 % )
Total registers : 9
Total pins : 41 / 475 ( 9 % )
Total virtual pins : 0
Total memory bits : 512 / 483,840 ( < 1 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )

tan.summary

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.188 ns
From           : single_port_ram:dev1|altsyncram:ram_rtl_0|altsyncram_tqb1:auto_generated|ram_block1a0~porta_address_reg5
To             : q[6]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 195.89 MHz ( period = 5.105 ns )
From           : single_port_ram:dev1|altsyncram:ram_rtl_0|altsyncram_tqb1:auto_generated|ram_block1a0~porta_address_reg5
To             : state.HALT
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------