Altera DE2 Project Diglab2

Download: design files

This lab illustrates the use of divide-by-N counters, decimal counters, and a simple hex counter.


Clock Divider

The clock divider takes the 50-MHz system clock input and generates a series of clock signals at different frequencies:

1 Mhz100 Khz10 Khz1 Khz100 hz10 hz1 hz

The clock array from the clock divider is called myclock in the top-level module (diglab2)

// Setup clock divider
wire [6:0] myclock;
clock_divider cdiv(CLOCK_50,RST,myclock);

The signals from the clock array are mapped to the external I/O connector, which can then be connected to an oscilloscope or other external instrument.

assign GPIO_0[6:0] = myclock;

The signals from 1 Hz to 1 kHz are also mapped to green LEDs. Only the 1 Hz and 10 Hz signals should be perceivable by the human eye.

// Connect clock divider to green LEDs
assign LEDG[4:0] = myclock[4:0];

The clock divider uses a divide-by-50 counter to reduce the frequency from 50 MHz to 1 MHz. Then divide-by-10 counters are used to reduce the frequency by succesive factors of ten.

Decimal Counter

Two decimal counters are controlled by the 1Hz clock and connected to two seven-segment-display digits.

// set up counters
wire [3:0] digit7, digit6;
wire ovr0, ovr1;

decimal_counter count0(digit6,ovr0,myclock[0],RST);
decimal_counter count1(digit7,ovr1,ovr0,RST);

// map to 7-segment displays

hex_7seg dsp0(digit6,HEX6);
hex_7seg dsp1(digit7,HEX7);

The overflow signals from the decimal counters are connected to two green LEDs:

assign LEDG[7] = ovr1;
assign LEDG[6] = ovr0;

Hexadecimal Counter

The following code defines a simple hexadecimal counter and maps it to a single seven-segment display.

reg [3:0] A;
always @ (posedge myclock[0])
   A <= A + 1'b1;

hex_7seg dsp2(A,HEX0); 


Verilog source and Quartus compilation report

Maintained by John Loomis, last updated 19 January 2008