# Project: diglab1

This lab illustrates the control of the LEDs, switches, and seven-segment displays.

## Exercises

1. Modify the starting program so that the word "HELP" is displayed on HEX7-HEX4.

2. Modify the starting program so that KEY3 enters the 8-bit value from SW[7:0] and displays it on HEX7-HEX6, KEY2 enters the 8-bit value from SW[7:0] and displays it on HEX5-HEX4, and KEY1 generates the logical and of A and B and displays the result in HEX1-HEX0. Blank the digits HEX3-HEX2.

3. Modify the previous program so that KEY1 generates a result determined by the control bits SW[3:0] as defined for the 74171 ALU chip.

4. Modify the previous program so that KEY1 causes the signed sum A+B or A-B to be displayed in HEX1-HEX0. If SW[0] is set, calculate the difference; otherwise calculate the sum. Set the green LED [7:4] to correspond to condition flag results: zero (Z), carry (C), negative (N), and overflow (V). If you have trouble calculating the overflow flag, start by setting it to zero and generate the other flags.

diglab1.v
hex_7seg.v

fit.summary
tan.summary

## Verilog Files

### `diglab1.v`

```module diglab1(
// Clock Input (50 MHz)
input  CLOCK_50,
//  Push Buttons
input  [3:0]  KEY,
//  DPDT Switches
input  [17:0]  SW,
//  7-SEG Displays
output  [6:0]  HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
//  LEDs
output  [8:0]  LEDG,  //  LED Green[8:0]
output  [17:0]  LEDR, //  LED Red[17:0]
//  GPIO Connections
inout  [35:0]  GPIO_0, GPIO_1
);

//  set all inout ports to tri-state
assign  GPIO_0    =  36'hzzzzzzzzz;
assign  GPIO_1    =  36'hzzzzzzzzz;

// Connect dip switches to red LEDs
assign LEDR[17:0] = SW[17:0];

// turn off green LEDs
assign LEDG[8:0] = 0;

reg [15:0] A;

// map to 7-segment displays

hex_7seg dsp0(A[3:0],HEX0);
hex_7seg dsp1(A[7:4],HEX1);
hex_7seg dsp2(A[11:8],HEX2);
hex_7seg dsp3(A[15:12],HEX3);

wire [6:0] blank = 7'b111_1111;

// blank remaining digits
assign HEX4 = blank;
assign HEX5 = blank;
assign HEX6 = blank;
assign HEX7 = blank;

// control (set) value of A, signal with KEY3

always @(negedge KEY[3])
A <= SW[15:0];

endmodule```

### `hex_7seg.v`

```module hex_7seg(hex_digit,seg);
input [3:0] hex_digit;
output [6:0] seg;
reg [6:0] seg;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off

always @ (hex_digit)
case (hex_digit)
4'h0: seg = 7'b1000000;
4'h1: seg = 7'b1111001;     // ---a----
4'h2: seg = 7'b0100100;     // |      |
4'h3: seg = 7'b0110000;     // f      b
4'h4: seg = 7'b0011001;     // |      |
4'h5: seg = 7'b0010010;     // ---g----
4'h6: seg = 7'b0000010;     // |      |
4'h7: seg = 7'b1111000;     // e      c
4'h8: seg = 7'b0000000;     // |      |
4'h9: seg = 7'b0011000;     // ---d----
4'ha: seg = 7'b0001000;
4'hb: seg = 7'b0000011;
4'hc: seg = 7'b1000110;
4'hd: seg = 7'b0100001;
4'he: seg = 7'b0000110;
4'hf: seg = 7'b0001110;
endcase

endmodule
```

## Quartus Compilation Summary

### `fit.summary`

```Fitter Status : Successful - Tue Jul 03 14:01:38 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : diglab1
Top-level Entity Name : diglab1
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Final
Total logic elements : 28 / 33,216 ( < 1 % )
Total registers : 16
Total pins : 178 / 475 ( 37 % )
Total virtual pins : 0
Total memory bits : 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )
```

### `tan.summary`

```--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.674 ns
From           : SW[15]
To             : A[15]
From Clock     : --
To Clock       : KEY[3]
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 7.449 ns
From           : A[6]
To             : HEX1[5]
From Clock     : KEY[3]
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 9.870 ns
From           : SW[15]
To             : LEDR[15]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.494 ns
From           : SW[3]
To             : A[3]
From Clock     : --
To Clock       : KEY[3]
Failed Paths   : 0

Type           : Total number of failed paths
Slack          :
Required Time  :
Actual Time    :
From           :
To             :
From Clock     :
To Clock       :
Failed Paths   : 0

--------------------------------------------------------------------------------------

```

Maintained by John Loomis, last updated Tue Jul 03 14:05:11 2007