Download: scomp.zip.
scomp.v
module scomp(clock, reset, memory_address, memory_data_out, register_A, pc, write_enable); input clock, reset; output [15:0] memory_data_out; output [15:0] register_A; output [7:0] pc; output [7:0] memory_address; //output [2:0] state; reg [2:0] state; reg [15:0] register_A; reg [7:0] pc; reg [1:0] control; reg [7:0] memory_address; reg [7:0] data_address; wire [15:0] alu_out; output write_enable; wire [7:0] opcode; assign opcode = memory_data_out[15:8]; parameter reset_pc = 3'd0, decode = 3'd1, execute = 3'd2, store1 = 3'd3, store2 = 3'd4; // instantiate memory (256 16-bit words) mem mem_component( .data (register_A), .address (memory_address), .wren (write_enable), .q (memory_data_out), .inclock (clock) ); // instantiate ALU ALU alu_component( .A(register_A), .B(memory_data_out), .C(alu_out), .control(control) ); assign write_enable = (state==store1); always case (state) reset_pc: memory_address <= 8'h00; decode: memory_address <= memory_data_out[7:0]; execute: memory_address <= pc; store1: memory_address <= data_address; store2: memory_address <= pc; default: memory_address <= 8'hff; endcase // finite state machine always @(posedge clock, negedge reset) begin if (~reset) state<=reset_pc; else case (state) reset_pc : begin pc <= 8'h00; register_A <= 16'h0000; state <= decode; end // decode opcode, increment program counter decode : begin if (opcode==8'h05) pc <= memory_data_out[7:0]; else if (opcode==8'h06 && register_A[15]) pc <= memory_data_out[7:0]; else pc <= pc + 8'h01; data_address <= memory_data_out[7:0]; // decode opcode case (opcode) 8'h01 : // load begin control <= 2'b01; state <= execute; end 8'h02 : // add begin control <= 2'b10; state <= execute; end 8'h03 : // subtract begin control <= 2'b11; state <= execute; end 8'h04 : // store begin control <= 2'b00; state <= store1; end default: begin control <= 2'b00; state <= decode; end endcase end // execute instruction, setup instruction address // Add opcode execute : begin register_A <= alu_out; state <= decode; end store1 : begin state <= store2; end // default state transition default : state <= decode; endcase end endmodule
mem.v
// megafunction wizard: %LPM_RAM_DQ% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: mem.v // Megafunction Name(s): // altsyncram // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 6.0 Build 178 04/27/2006 SJ Full Version // ************************************************************ //Copyright (C) 1991-2006 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module mem ( address, data, inclock, wren, q); input [7:0] address; input [15:0] data; input inclock; input wren; output [15:0] q; wire [15:0] sub_wire0; wire [15:0] q = sub_wire0[15:0]; altsyncram altsyncram_component ( .wren_a (wren), .clock0 (inclock), .address_a (address), .data_a (data), .q_a (sub_wire0), .aclr0 (1'b0), .aclr1 (1'b0), .address_b (1'b1), .addressstall_a (1'b0), .addressstall_b (1'b0), .byteena_a (1'b1), .byteena_b (1'b1), .clock1 (1'b1), .clocken0 (1'b1), .clocken1 (1'b1), .data_b (1'b1), .q_b (), .rden_b (1'b1), .wren_b (1'b0)); defparam altsyncram_component.clock_enable_input_a = "BYPASS", altsyncram_component.clock_enable_output_a = "BYPASS", altsyncram_component.init_file = "program.mif", altsyncram_component.intended_device_family = "Cyclone II", altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", altsyncram_component.lpm_type = "altsyncram", altsyncram_component.numwords_a = 256, altsyncram_component.operation_mode = "SINGLE_PORT", altsyncram_component.outdata_aclr_a = "NONE", altsyncram_component.outdata_reg_a = "UNREGISTERED", altsyncram_component.power_up_uninitialized = "FALSE", altsyncram_component.widthad_a = 8, altsyncram_component.width_a = 16, altsyncram_component.width_byteena_a = 1; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" // Retrieval info: PRIVATE: AclrByte NUMERIC "0" // Retrieval info: PRIVATE: AclrData NUMERIC "0" // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" // Retrieval info: PRIVATE: Clken NUMERIC "0" // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MIFfilename STRING "program.mif" // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: RegAddr NUMERIC "1" // Retrieval info: PRIVATE: RegData NUMERIC "1" // Retrieval info: PRIVATE: RegOutput NUMERIC "0" // Retrieval info: PRIVATE: SingleClock NUMERIC "0" // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" // Retrieval info: PRIVATE: WidthAddr NUMERIC "8" // Retrieval info: PRIVATE: WidthData NUMERIC "16" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: INIT_FILE STRING "program.mif" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0] // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] // Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT NODEFVAL inclock // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren // Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 // Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 inclock 0 0 0 0 // Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: GEN_FILE: TYPE_NORMAL mem.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL mem.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL mem.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL mem.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL mem_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL mem_bb.v TRUE
ALU.v
/* * * control * 0 0 C = A * 0 1 C = B * 1 0 C = A + B * 1 1 C = A - B */ module ALU(A,B,C,control); input [15:0] A, B; output [15:0] C; input [1:0] control; wire subtract, mux1, mux2; assign {mux2, mux1} = control; assign subtract = mux1; wire [15:0] D,sum; assign D = (subtract? ~B: B); assign sum = A + D + subtract; assign C = (mux2? sum: (mux1? B: A) ); endmodule
program.mif
DEPTH = 256; % Memory depth and width are required % WIDTH = 16; % Enter a decimal number % ADDRESS_RADIX = HEX; % Address and value radixes are optional % DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless % % otherwise specified, radixes = HEX % -- Specify values for addresses, which can be single address or range CONTENT BEGIN [00..FF] : 0000; % Range--Every address from 00 to FF = 0000 (Default) % 00 : 0110; % LOAD AC with MEM(10) % 01 : 0211; % ADD MEM(11) to A % 02 : 0413; % STORE AC in MEM(13) % 03 : 0112; % Clear AC % 04 : 0113; % LOAD AC with MEM(13) check for new value of 0ABC % 05 : 0505; % JUMP to 05 (loop forever) % 10 : 0AAA; % Data Value % 11 : 0012; % Data Value % 12 : 0000; % Data Value % 13 : 0000; % Data Value - should be 0ABC after running program % END ;
fit.summary
Fitter Status : Successful - Tue Jul 17 15:01:46 2007 Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version Revision Name : scomp Top-level Entity Name : scomp Family : Cyclone II Device : EP2C35F672C6 Timing Models : Final Total logic elements : 136 / 33,216 ( < 1 % ) Total registers : 39 Total pins : 51 / 475 ( 11 % ) Total virtual pins : 0 Total memory bits : 4,096 / 483,840 ( < 1 % ) Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % ) Total PLLs : 0 / 4 ( 0 % )
tan.summary
-------------------------------------------------------------------------------------- Timing Analyzer Summary -------------------------------------------------------------------------------------- Type : Worst-case tsu Slack : N/A Required Time : None Actual Time : 2.536 ns From : reset To : data_address[6] From Clock : -- To Clock : clock Failed Paths : 0 Type : Worst-case tco Slack : N/A Required Time : None Actual Time : 11.679 ns From : mem:mem_component|altsyncram:altsyncram_component|altsyncram_l2d1:auto_generated|ram_block1a0~porta_address_reg7 To : memory_address[6] From Clock : clock To Clock : -- Failed Paths : 0 Type : Worst-case th Slack : N/A Required Time : None Actual Time : -0.718 ns From : reset To : register_A[15]~reg0 From Clock : -- To Clock : clock Failed Paths : 0 Type : Clock Setup: 'clock' Slack : N/A Required Time : None Actual Time : 137.95 MHz ( period = 7.249 ns ) From : mem:mem_component|altsyncram:altsyncram_component|altsyncram_l2d1:auto_generated|ram_block1a0~porta_address_reg7 To : register_A[15]~reg0 From Clock : clock To Clock : clock Failed Paths : 0 Type : Total number of failed paths Slack : Required Time : Actual Time : From : To : From Clock : To Clock : Failed Paths : 0 --------------------------------------------------------------------------------------
Maintained by John Loomis, last updated Tue Jul 17 15:03:00 2007