ECE444 Advanced Digital Design
Assignment 1

The objective of this assignment is to verify that each class member can do the following:

  1. Setup and run a Verilog design in Quartus and generate a simulation. You may use the multiplier example from class.

  2. Setup and run a project on the DE2 board. You should demonstrate the project to the instructor. You may use the example project from class that allowed the user to set the segments of the left-most 7-segment display and show the corresponding hex code on the right-most segments.

  3. Setup and run a Verilog project (with testbench) and simulation in Silos. You may use example 2.34 from the textbook (which we did in class).

The supporting files for each project should be packaged in a separate folder. The contents of Quartus folders should have non-essential files removed. DE2 projects should retain the .sof file. You should use qdoc to document Quartus projects. The folders should contain all necessary files required to launch and compile a Quartus project with a single "Start Compilation" action.

You should produce a Word document describing the basic objectives, design elements, and results of simulation (if appropriate). This narrative should have meaningful figures and extractions of Verilog code. The report should not contain raw, uninterpreted computer output.


Maintained by John Loomis, last updated 8 September 2009