The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design ram1.v. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design ram1.v has one read/write port. The read/write port has 32 words of 8 bits each. The output of the read/write port is registered by clock.
The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.
The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. Actual write into the RAM happens at the falling edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. During a write cycle, the new data flows through to the output.