ramproj.v
module ramproj #(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=5) ( input [(DATA_WIDTH-1):0] data, input [(ADDR_WIDTH-1):0] addr, input we, clk, output [(DATA_WIDTH-1):0] q ); single_port_ram dev(data,addr,we,clk,q); endmodule
single_port_ram.v
// Quartus II Verilog Template // Single port RAM with single read/write address module single_port_ram #(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=5) ( input [(DATA_WIDTH-1):0] data, input [(ADDR_WIDTH-1):0] addr, input we, clk, output [(DATA_WIDTH-1):0] q ); // Declare the RAM variable reg [DATA_WIDTH-1:0] ram[0:2**ADDR_WIDTH-1]; // Variable to hold the registered read address reg [ADDR_WIDTH-1:0] addr_reg; always @ (posedge clk) begin // Write if (we) ram[addr] <= data; addr_reg <= addr; end // Continuous assignment implies read returns NEW data. // This is the natural behavior of the TriMatrix memory // blocks in Single Port mode. assign q = ram[addr_reg]; endmodule
fit.summary
Fitter Status : Successful - Mon Sep 21 09:51:45 2009 Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition Revision Name : ramproj Top-level Entity Name : ramproj Family : Cyclone II Device : EP2C35F484C8 Timing Models : Final Total logic elements : 0 / 33,216 ( 0 % ) Total combinational functions : 0 / 33,216 ( 0 % ) Dedicated logic registers : 0 / 33,216 ( 0 % ) Total registers : 0 Total pins : 23 / 322 ( 7 % ) Total virtual pins : 0 Total memory bits : 256 / 483,840 ( < 1 % ) Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % ) Total PLLs : 0 / 4 ( 0 % )
tan.summary
-------------------------------------------------------------------------------------- Timing Analyzer Summary -------------------------------------------------------------------------------------- Type : Worst-case tsu Slack : N/A Required Time : None Actual Time : 5.633 ns From : we To : single_port_ram:dev|altsyncram:ram_rtl_0|altsyncram_n861:auto_generated|ram_block1a0~porta_we_reg From Clock : -- To Clock : clk Failed Paths : 0 Type : Worst-case tco Slack : N/A Required Time : None Actual Time : 14.996 ns From : single_port_ram:dev|altsyncram:ram_rtl_0|altsyncram_n861:auto_generated|ram_block1a0~porta_address_reg4 To : q[0] From Clock : clk To Clock : -- Failed Paths : 0 Type : Worst-case th Slack : N/A Required Time : None Actual Time : -3.911 ns From : data[0] To : single_port_ram:dev|altsyncram:ram_rtl_0|altsyncram_n861:auto_generated|ram_block1a0~porta_datain_reg0 From Clock : -- To Clock : clk Failed Paths : 0 Type : Clock Setup: 'clk' Slack : N/A Required Time : None Actual Time : Restricted to 163.03 MHz ( period = 6.134 ns ) From : single_port_ram:dev|altsyncram:ram_rtl_0|altsyncram_n861:auto_generated|ram_block1a0~porta_datain_reg7 To : single_port_ram:dev|altsyncram:ram_rtl_0|altsyncram_n861:auto_generated|ram_block1a7~porta_memory_reg0 From Clock : clk To Clock : clk Failed Paths : 0 Type : Total number of failed paths Slack : Required Time : Actual Time : From : To : From Clock : To Clock : Failed Paths : 0 --------------------------------------------------------------------------------------
Maintained by John Loomis, last updated Wed Sep 23 09:08:35 2009