reg_file.v
module reg_file #(parameter BITS = 32) ( input clock, write_enable, input [BITS-1:0] dc, input [4:0] ra,rb,rc, output [BITS-1:0] qa,qb ); wire wren = write_enable && rc; reg_ram A( .clock(clock), .data(dc), .rdaddress(ra), .wraddress(rc), .wren(wren), .q(qa) ); reg_ram B( .clock(clock), .data(dc), .rdaddress(rb), .wraddress(rc), .wren(wren), .q(qb) ); endmodule
fit.summary
Fitter Status : Successful - Tue Sep 29 21:38:08 2009 Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition Revision Name : reg_file Top-level Entity Name : reg_file Family : Cyclone II Device : EP2C35F672C6 Timing Models : Final Total logic elements : 2 / 33,216 ( < 1 % ) Total combinational functions : 2 / 33,216 ( < 1 % ) Dedicated logic registers : 0 / 33,216 ( 0 % ) Total registers : 0 Total pins : 113 / 475 ( 24 % ) Total virtual pins : 0 Total memory bits : 2,048 / 483,840 ( < 1 % ) Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % ) Total PLLs : 0 / 4 ( 0 % )
tan.summary
-------------------------------------------------------------------------------------- Timing Analyzer Summary -------------------------------------------------------------------------------------- Type : Worst-case tsu Slack : N/A Required Time : None Actual Time : 5.455 ns From : rc[4] To : reg_ram:B|altsyncram:altsyncram_component|altsyncram_g8r1:auto_generated|ram_block1a0~porta_we_reg From Clock : -- To Clock : clock Failed Paths : 0 Type : Worst-case tco Slack : N/A Required Time : None Actual Time : 11.974 ns From : reg_ram:B|altsyncram:altsyncram_component|altsyncram_g8r1:auto_generated|ram_block1a0~portb_address_reg4 To : qb[16] From Clock : clock To Clock : -- Failed Paths : 0 Type : Worst-case th Slack : N/A Required Time : None Actual Time : -3.105 ns From : dc[27] To : reg_ram:A|altsyncram:altsyncram_component|altsyncram_g8r1:auto_generated|ram_block1a0~porta_datain_reg27 From Clock : -- To Clock : clock Failed Paths : 0 Type : Clock Setup: 'clock' Slack : N/A Required Time : None Actual Time : Restricted to 235.07 MHz ( period = 4.254 ns ) From : reg_ram:B|altsyncram:altsyncram_component|altsyncram_g8r1:auto_generated|ram_block1a0~porta_datain_reg31 To : reg_ram:B|altsyncram:altsyncram_component|altsyncram_g8r1:auto_generated|ram_block1a31~porta_memory_reg0 From Clock : clock To Clock : clock Failed Paths : 0 Type : Total number of failed paths Slack : Required Time : Actual Time : From : To : From Clock : To Clock : Failed Paths : 0 --------------------------------------------------------------------------------------
Maintained by John Loomis, last updated Tue Sep 29 21:39:14 2009