reg_file.v
module reg_file #(parameter BITS = 32) ( input clock, write_enable, input [BITS-1:0] dc, input [4:0] ra,rb,rc, output [BITS-1:0] qa,qb ); reg [BITS-1:0] pa[0:31], pb[0:31]; initial begin $readmemh("reg_init.txt", pa); $readmemh("reg_init.txt", pb); end // RAM A reg [4:0] addr_a; always @(posedge clock) begin if (write_enable && rc) pa[rc] <= dc; addr_a <= ra; end assign qa = pa[addr_a]; // RAM B reg [4:0] addr_b; always @(posedge clock) begin if (write_enable && rc) pb[rc] <= dc; addr_b <= rb; end assign qb = pb[addr_b]; endmodule
fit.summary
Fitter Status : Successful - Tue Sep 29 20:38:25 2009 Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition Revision Name : reg_file Top-level Entity Name : reg_file Family : Cyclone II Device : EP2C35F672C6 Timing Models : Final Total logic elements : 81 / 33,216 ( < 1 % ) Total combinational functions : 72 / 33,216 ( < 1 % ) Dedicated logic registers : 48 / 33,216 ( < 1 % ) Total registers : 48 Total pins : 113 / 475 ( 24 % ) Total virtual pins : 0 Total memory bits : 2,048 / 483,840 ( < 1 % ) Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % ) Total PLLs : 0 / 4 ( 0 % )
tan.summary
-------------------------------------------------------------------------------------- Timing Analyzer Summary -------------------------------------------------------------------------------------- Type : Worst-case tsu Slack : N/A Required Time : None Actual Time : 6.507 ns From : rc[0] To : altsyncram:pb_rtl_1|altsyncram_ivi1:auto_generated|ram_block1a0~porta_we_reg From Clock : -- To Clock : clock Failed Paths : 0 Type : Worst-case tco Slack : N/A Required Time : None Actual Time : 13.003 ns From : altsyncram:pa_rtl_0|altsyncram_hvi1:auto_generated|ram_block1a0~portb_address_reg4 To : qa[16] From Clock : clock To Clock : -- Failed Paths : 0 Type : Worst-case th Slack : N/A Required Time : None Actual Time : -3.226 ns From : dc[14] To : altsyncram:pb_rtl_1|altsyncram_ivi1:auto_generated|ram_block1a0~porta_datain_reg14 From Clock : -- To Clock : clock Failed Paths : 0 Type : Clock Setup: 'clock' Slack : N/A Required Time : None Actual Time : Restricted to 235.07 MHz ( period = 4.254 ns ) From : altsyncram:pb_rtl_1|altsyncram_ivi1:auto_generated|ram_block1a0~porta_datain_reg31 To : altsyncram:pb_rtl_1|altsyncram_ivi1:auto_generated|ram_block1a31~porta_memory_reg0 From Clock : clock To Clock : clock Failed Paths : 0 Type : Total number of failed paths Slack : Required Time : Actual Time : From : To : From Clock : To Clock : Failed Paths : 0 --------------------------------------------------------------------------------------
Maintained by John Loomis, last updated Tue Sep 29 20:46:21 2009