	   ==================================================
	   SILOS III Logic Simulation Demonstration Version
				and
	   HyperFault Fault Simulation Demonstration Version
	   ==================================================

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SPECIAL NOTICES:

1)	The SILOS III Demonstration Program and the 
	HyperFault Demonstration Program are
	designed to be used for demonstration
	purposes only.  The program has specific
	limitations to prevent usage for commercial
	purposes.  There are features and capabilities
	which are intentionally reduced or disabled.

	The demonstration version is limited to 200 gates
	and 350 lines of behavioral code.

2)  HTML on-line help support is available for the SILOS III User's Manual,
	HyperFault User's Manual, SDF Manual, and the Verilog LRM OVI version 1.0.
	This provides on-line help for Unix platforms.

	Please note that the HTML language does not support the tab character.  
	This means that the conversion from Microsoft Word to HTML may run some 
	words together that previously were separated by a tab.

	To start the HTML on-line help, use the file "helpcontents1.htm" located in
	each of the on-line help subdirectories for HTML:  sse_htm, hse_htm, verilog_htm,
	and sdf_htm.



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SILOS III is a logic simulator used for the design
and verification of electronic circuits.  The SILOS Simulation
Environment (SSE) is the user interface for SILOS III.

HyperFault is a fault simulator used to fault grade test
vectors for ASIC designs.  The HyperFault Simulation
Environment (HSE) is the user interface for HyperFault.

SILOS III and HyperFault support the Verilog Hardware Description
Language, the Programming Language Interface (PLI), and the 
Standard Delay File (SDF) format.

RELEASE NOTES:

1)  Notice to EXCEED users:

	Exceed is an X-Server that runs on PC's and allows you to view 
	the GUI on your PC while the SSE or HSE is executing on Sun.

	The SSE or HSE works with Exceed 6.0, however, if you installed 
	Exceed 	with a 75dpi or larger font, some of the dialog windows 
	may not fit on you screen. For the entire window to be visible, 
	change the font to the 100dpi font provided.  Note it may be 
	necessary for you to pull this font from the Exceed CD, and then add 
	it to the fonts Exceed allows you to select from. Also, if your 
	display is setup with little resolution (600X600), it may be 
	necessary to increase the resolution above 1000. 



SYSTEM REQUIREMENTS: 

1) 	For the release version, at least 16 MB of available memory 
	is recommended.  Memory usage varies depending on the design.  
	Generally, 100k gates will fit into about 40 - 60 megabytes of 
	RAM memory for logic simulation.  You need to allow additional
	memory for the test vectors, for the Graphical User Interface (GUI),
	and for your operating system. 

	For fault simulation, you should allow at least 2x the amount of 
	memory used for logic simulation.  For fault simulation, additional 
	memory enables you to run more 	concurrent faults, which can reduce 
	the fault simulation run time.

2)	The release installation requires less than 90 Mb of disk space.  
	The amount of disk needed during simulation will vary based 
	on the size of the circuit and its activity. 

3)      SILOS III:  Windows 98, Windows 2000, Windows NT (version 4.0 or 
		    higher),  Linux, or Solaris.

      	HyperFault: Windows NT (version 4.0 or higher), or 
		    Solaris.

4)	The CD-ROM supports the following platform on the PC:
		-  Intel P5 or higher.

	The CD-ROM supports the following platform on the workstation:
		-  Solaris.


DISTRIBUTION MEDIA:

SILOS III and HyperFault are distributed on CD-ROM.  The CD-ROM includes 
all of the files necessary to install SILOS III on systems running 
Windows 98, Windows 2000, Windows NT, Linux, or Solaris, and HyperFault on 
Windows NT and Unix.
   
INSTALLATION:

To install SILOS III and HyperFault from the CD-ROM, see the readme.txt 
file at the top level of the CD-ROM.


FILE LIST FOR INSTALLATION DIRECTORY:

The files have been compressed and can only be installed by running the 
setup program on the CD-ROM.  The following is
a list of files for the release and a short summary as to
their purpose.


TOP LEVEL OF INSTALLATION DIRECTORY


FSM.DLL		-	DLL file for the Finite State Machine.

HSE.EXE     	-       HyperFault Simulation Environment program for fault 
			simulation.  (Windows NT)

HSE.EXE.LOCAL	-	Flag for Windows 2000 to find the correct .DLL file.

HSE.LIB     	-       HSE import library (Windows NT).  Must be used to 
			create HSE.EXE PLI DLL's.

LM_SILOS.DLL	-	FLEXlm program dll.

LM_SSE.DLL	-	FLEXlm program dll.

LMGR327A.DLL 	-	FLEXlm program dll.

MSVCRT.DLL 	-	Program dll.

OLEAUT32.DLL 	-	Program dll.

OLEPRO32.DLL 	-	Program dll.

README.TXT     	-       This file.

SSE.EXE     	-       SILOS Simulation Environment program for logic 
			simulation.  (Windows NT, Windows 98, and Windows 95)

SSE.LIB     	-       SSE import library (Windows NT, Windows 95, and Windows 98).
                      	Must be used to create SSE.EXE PLI DLL's.


HELP SUBDIRECTORY

SSE.HLP     	-       SILOS III User's Manual and Tutorial is provided 
			as an on-line help file.

HSE.HLP     	-      	HyperFault User's Manual and Tutorial is provided 
			as an on-line help file.

VERILOG.HLP    	-      	Open Verilog International (OVI) Language Reference 
			Manual version 1.0 provided as an on-line help file.

SDF.HLP		-      	OVI Standard Delay Format (SDF) Manual version 2.0
			provided as an on-line help file.




EXAMPLES SUBDIRECTORY

ANALOG.SPJ      -      	Project file for Analog to Digital converter 
			circuit that models the analog portion at 
			the behavioral level and the digital portion  
			at the gate level.  To run this example, see
			"Tutorial/Analog Behavioral Modeling (AHDL)"
			in the on-line help for the SSE.  

FLTSIM.SPJ	-	Project file for circuit that demonstrates
			features for fault simulation.  To run this 
			example, see "Tutorial/Fault Simulation 
			Examples Overview" in the on-line help for 
			the HSE.

GATE.SPJ	-	Project file for circuit that demonstrates
			traceback at the gate level.  Traceback
			is useful for finding problems after 
			synthesis.
			To run this example, see "Tutorial/Gate Level
			Debugging" in the on-line help for the SSE.

RTL_.SPJ	-	Project file for circuit that demonstrates
			features for debugging an RTL design.
			To run this example, see "Tutorial/RTL 
			(Behavioral)  Debugging" in the on-line help 
			for the SSE.

RTL_ERR.SPJ	-	Project file for circuit that shows how
			to automatically open the source file for
			displaying a syntax error.
			To run this example, see "Tutorial/Error
			Reporting" in the on-line help for the SSE.
			 
VENDING.SPJ	-	Project file for circuit that demonstrates
			features for a finite state machine.  To run this 
			example, see "Tutorial/Finite State Machine Entry" 
			in the on-line help for the SSE.

*******************
IMPORTANT NOTICE
*******************


All versions of SILOS III, including this limited demonstration license, 
shall be treated as the confidential property of SIMUCAD, Inc.

This limited demonstration license is granted by SIMUCAD, Inc. and is
subject to the following conditions and limitations:

1)      There are no restrictions on making copies of this demonstration
	version of SILOS III (software and documentation).

2)      No person will decompile or disassemble this program or by any
	other similar means of reverse engineering undertake to discover
	the ideas, information and algorithms embodied in this program.

3)      This license is granted solely for the purpose of evaluating 
	SILOS III and use of this license for commercial purposes is
	strictly forbidden.



				WARRANTY

SIMUCAD makes no warranty of any kind, express or implied including,
without limitation, any warranties of merchantability and/or fitness
for a particular purpose. Simucad shall not be liable for any damages, 
whether direct, indirect, special or consequential arising from a
failure of the program to operate in the manner desired by the user.
Simucad shall not be liable for any damage to any property that may
be caused directly or indirectly by the software or duplication of
the software.


IN NO EVENT WILL SIMUCAD BE LIABLE FOR ANY DAMAGES INCLUDING ANY
LOST PROFITS, LOST SAVINGS OR OTHER INCIDENTAL OR CONSEQUENTIAL
DAMAGES ARISING OUT OF INABILITY TO USE THE PROGRAM, OR FOR ANY
OTHER CLAIM BY ANY OTHER PARTY.


COPYRIGHT NOTICES:

SIMUCAD and SILOS are registered trademarks of and SILOS III, HyperFault,
SILOS II, SILOS, P/C-SILOS, SILOS Simulation Environment and the Silos Data
Analyzer are trademarks of SIMUCAD, Inc.

Verilog is a registered trademark of Cadence Design Systems Inc.  
Other company and product names may be trademarks of the respective 
company with which they are associated. 

