Flow Status : Successful - Tue Feb 07 13:22:45 2006 Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version Revision Name : scomp Top-level Entity Name : scomp Family : FLEX10K Device : EPF10K70RC240-4 Timing Models : Final Met timing requirements : N/A Total logic elements : 137 / 3,744 ( 3 % ) Total pins : 58 / 189 ( 30 % ) Total memory bits : 4,096 / 18,432 ( 22 % )
+----------------------------------------------------------+ ; Fitter Resource Usage Summary ; +--------------------------------+-------------------------+ ; Resource ; Usage ; +--------------------------------+-------------------------+ ; Registers ; 41 / 3,744 ( 1 % ) ; ; Total LABs ; 0 / 468 ( 0 % ) ; ; Logic elements in carry chains ; 23 ; ; User inserted logic elements ; 0 ; ; I/O pins ; 58 / 189 ( 30 % ) ; ; -- Clock pins ; 1 ; ; -- Dedicated input pins ; 1 / 4 ( 25 % ) ; ; Global signals ; 2 ; ; EABs ; 2 / 9 ( 22 % ) ; ; Total memory bits ; 4,096 / 18,432 ( 22 % ) ; ; Total RAM block bits ; 4,096 / 18,432 ( 22 % ) ; ; Maximum fan-out node ; clock ; ; Maximum fan-out ; 57 ; ; Total fan-out ; 773 ; ; Average fan-out ; 3.66 ; +--------------------------------+-------------------------+
+---------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +-----------------------------------+---------+ ; Resource ; Usage ; +-----------------------------------+---------+ ; Total logic elements ; 137 ; ; Total combinational functions ; 137 ; ; -- Total 4-input functions ; 59 ; ; -- Total 3-input functions ; 53 ; ; -- Total 2-input functions ; 18 ; ; -- Total 1-input functions ; 7 ; ; -- Total 0-input functions ; 0 ; ; Combinational cells for routing ; 0 ; ; Total registers ; 41 ; ; Total logic cells in carry chains ; 23 ; ; I/O pins ; 58 ; ; Total memory bits ; 4096 ; ; Maximum fan-out node ; clock ; ; Maximum fan-out ; 57 ; ; Total fan-out ; 773 ; ; Average fan-out ; 3.66 ; +-----------------------------------+---------+
+------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ ; Total registers ; 41 ; ; Number of registers using Synchronous Clear ; 0 ; ; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Asynchronous Clear ; 8 ; ; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Clock Enable ; 33 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+
Worst-case tco: 36.2 ns (for a memory access)
-------------------------------------------------------------------------------------- Timing Analyzer Summary -------------------------------------------------------------------------------------- Type : Worst-case tsu Slack : N/A Required Time : None Actual Time : 16.100 ns From : reset To : register_A[1]~reg0 From Clock : To Clock : clock Failed Paths : 0 Type : Worst-case tco Slack : N/A Required Time : None Actual Time : 36.200 ns From : mem:mem_component|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[9]~reg_wa7 To : memory_data_out[9] From Clock : clock To Clock : Failed Paths : 0 Type : Worst-case th Slack : N/A Required Time : None Actual Time : -9.400 ns From : reset To : pc[7]~reg0 From Clock : To Clock : clock Failed Paths : 0 Type : Clock Setup: 'clock' Slack : N/A Required Time : None Actual Time : 15.72 MHz ( period = 63.600 ns ) From : mem:mem_component|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[0]~reg_wa7 To : register_A[15]~reg0 From Clock : clock To Clock : clock Failed Paths : 0 Type : Total number of failed paths Slack : Required Time : Actual Time : From : To : From Clock : To Clock : Failed Paths : 0 --------------------------------------------------------------------------------------
module scomp(clock, reset, memory_address, memory_data_out, register_A, pc, state); input clock, reset; output [15:0] memory_data_out; output [15:0] register_A; output [7:0] pc; output [7:0] memory_address; output [7:0] state; reg [7:0] state; reg write_enable; reg [15:0] register_A; reg [7:0] pc, memory_address; parameter reset_pc = 8'h80, fetch = 8'h81, store1 = 8'h82; // instantiate memory (256 16-bit words) mem mem_component( .data (register_A), .address (memory_address), .we (write_enable), .q (memory_data_out), .inclock (clock) ); // finite state machine always @(negedge clock, posedge reset) begin if (reset) state<=reset_pc; else case (state) reset_pc : begin pc <= 8'h00; write_enable <= 1'b0; memory_address <= 8'h00; register_A <= 16'h0000; state <= fetch; end // latch instruction address, increment program counter fetch : begin pc <= pc + 8'h01; // fetch instruction (on posedge), setup data address memory_address <= memory_data_out[7:0]; state <= memory_data_out[15:8]; end // execute instruction, setup instruction address // Add opcode 8'h00 : begin register_A <= register_A + memory_data_out; memory_address <= pc; state <= fetch; end // store 8'h01 : begin write_enable <= 1'b1; state <= store1; end store1 : begin memory_address <= pc; write_enable <= 1'b0; state <= fetch; end // load 8'h02 : begin register_A <= memory_data_out; memory_address <= pc; state <= fetch; end // jump 8'h03 : begin pc <= memory_address; state <= fetch; end // unrecognized state/opcode default : begin memory_address <= pc; state <= fetch; end endcase end endmodule
// megafunction wizard: %LPM_RAM_DQ% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: lpm_ram_dq // ============================================================ // File Name: mem.v // Megafunction Name(s): // lpm_ram_dq // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 5.0 Build 148 04/26/2005 SJ Full Version // ************************************************************ //Copyright (C) 1991-2005 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module mem ( address, we, inclock, data, q); input [7:0] address; input we; input inclock; input [15:0] data; output [15:0] q; wire [15:0] sub_wire0; wire [15:0] q = sub_wire0[15:0]; lpm_ram_dq lpm_ram_dq_component ( .address (address), .inclock (inclock), .data (data), .we (we), .q (sub_wire0) // synopsys translate_off , .outclock () // synopsys translate_on ); defparam lpm_ram_dq_component.intended_device_family = "FLEX10K", lpm_ram_dq_component.lpm_width = 16, lpm_ram_dq_component.lpm_widthad = 8, lpm_ram_dq_component.lpm_indata = "REGISTERED", lpm_ram_dq_component.lpm_address_control = "REGISTERED", lpm_ram_dq_component.lpm_outdata = "UNREGISTERED", lpm_ram_dq_component.lpm_file = "program.mif", lpm_ram_dq_component.lpm_type = "LPM_RAM_DQ"; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: WidthData NUMERIC "16" // Retrieval info: PRIVATE: WidthAddr NUMERIC "8" // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" // Retrieval info: PRIVATE: SingleClock NUMERIC "0" // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" // Retrieval info: PRIVATE: RegData NUMERIC "1" // Retrieval info: PRIVATE: RegAddr NUMERIC "1" // Retrieval info: PRIVATE: RegOutput NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: AclrByte NUMERIC "0" // Retrieval info: PRIVATE: AclrData NUMERIC "0" // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" // Retrieval info: PRIVATE: Clken NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" // Retrieval info: PRIVATE: RegAdd NUMERIC "1" // Retrieval info: PRIVATE: OutputRegistered NUMERIC "0" // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" // Retrieval info: PRIVATE: MIFfilename STRING "program.mif" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "FLEX10K" // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "FLEX10K" // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" // Retrieval info: CONSTANT: LPM_WIDTHAD NUMERIC "8" // Retrieval info: CONSTANT: LPM_INDATA STRING "REGISTERED" // Retrieval info: CONSTANT: LPM_ADDRESS_CONTROL STRING "REGISTERED" // Retrieval info: CONSTANT: LPM_OUTDATA STRING "UNREGISTERED" // Retrieval info: CONSTANT: LPM_FILE STRING "program.mif" // Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_RAM_DQ" // Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0] // Retrieval info: USED_PORT: we 0 0 0 0 INPUT VCC we // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] // Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT NODEFVAL inclock // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] // Retrieval info: CONNECT: @address 0 0 8 0 address 0 0 8 0 // Retrieval info: CONNECT: @we 0 0 0 0 we 0 0 0 0 // Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 // Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 // Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 // Retrieval info: LIBRARY: lpm lpm.lpm_components.all // Retrieval info: GEN_FILE: TYPE_NORMAL mem.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL mem.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL mem.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL mem.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL mem_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL mem_bb.v TRUE
DEPTH = 256; % Memory depth and width are required %
WIDTH = 16; % Enter a decimal number %
ADDRESS_RADIX = HEX; % Address and value radixes are optional %
DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless %
% otherwise specified, radixes = HEX %
-- Specify values for addresses, which can be single address or range
CONTENT
BEGIN
[00..FF] : 0000; % Range--Every address from 00 to FF = 0000 (Default) %
00 : 0210; % LOAD AC with MEM(10) %
01 : 0011; % ADD MEM(11) to A %
02 : 0113; % STORE AC in MEM(13) %
03 : 0212; % Clear AC %
04 : 0213; % LOAD AC with MEM(13) check for new value of 0ABC %
05 : 0305; % JUMP to 05 (loop forever) %
10 : 0AAA; % Data Value %
11 : 0012; % Data Value %
12 : 0000; % Data Value %
13 : 0000; % Data Value - should be 0ABC after running program %
END ;
Maintained by John Loomis, last updated 7 Feb 2006