The length of time for which data that feeds a register via its data or enable input(s) must be present at an input pin before the clock signal that clocks the register is asserted at the clock pin.
tSU =
<pin to register
delay> +
<micro setup delay>
-
<clock to destination register delay>
The maximum time required to obtain a valid output at an output pin that is fed by a register after a clock signal transition on an input pin that clocks the register. This time always represents an external pin-to-pin delay.
tCO =
<clock to source register delay> +
<micro clock to output delay> +
<register to pin delay>
The minimum length of time for which data that feeds a register via its data or enable input(s) must be retained at an input pin after the clock signal that clocks the register is asserted at the clock pin.
tH =
<clock to destination register delay> +
<micro hold delay of destination register> -
<pin to register delay>
The maximum clock frequency that can be achieved without violating internal setup (tSU) and hold (tH) time requirements.
fMAX =
1/(
<register to register delay> -
<clock skew delay> +
<micro setup delay> +
<micro clock to output delay>)
Where clock skew delay is calculated from
<clock to destination register delay> -
<clock to source register delay>
The time required for a signal from an input pin to propagate through combinational logic and appear at an external output pin.
Altera Quartus® II software help
Maintained by John Loomis, last updated 7 Feb 2006