Project: jsim1

jsim1.v

module jsim1 
#(parameter DATA_WIDTH=16, parameter ADDR_WIDTH=5)
(
    input clk, reset_n,
    output reg [(DATA_WIDTH-1):0] data,
    output [(ADDR_WIDTH-1):0] addr,
    output we,
    output  [(DATA_WIDTH-1):0] q,
    output reg [4:0] pc,
    output reg state, 
    output memory_access
);

single_port_ram dev(
    .data(data),
    .addr(addr),
    .we(we),
    .clk(clk),
    .q(q)
);

//reg [4:0] pc;

//wire [2:0] opcode = q[15:13];
wire [2:0] opcode;
wire [4:0] immed;

assign opcode = (state==IFE? q[15:13]: 3'h0);
assign immed = (state==IFE? q[4:0]: 3'h0);

//reg state;
parameter IFE = 1'b0,
    MEM = 1'b1;
    
parameter SW = 3'h4, LW = 3'h5;

//wire memory_access;
assign we = (opcode==SW);
assign memory_access = (we || opcode==LW);


wire [4:0] nextpc = pc + 1'b1;

assign addr = (memory_access? immed: nextpc);


always @(posedge clk, negedge reset_n)
begin
  if (!reset_n)
  begin
   pc <= 5'hFF;
   state <= IFE;
   end
  else 
    case (state)
    IFE:
    begin
      if (memory_access) state <=MEM;
      else state <= IFE;
      //if (memory_access) addr <= q[4:0];
      //else addr <= nextpc;
      if (!memory_access) pc <= nextpc;
      data <= 16'h0000;
    end
    MEM:
    begin
       //addr <= nextpc;
       pc <= nextpc;
       state <= IFE;
      data <= q;
    end
  endcase
end

endmodule

single_port_ram.v

// Quartus II Verilog Template
// Single port RAM with single read/write address 

module single_port_ram 
#(parameter DATA_WIDTH=16, parameter ADDR_WIDTH=5)
(
    input [(DATA_WIDTH-1):0] data,
    input [(ADDR_WIDTH-1):0] addr,
    input we, clk,
    output [(DATA_WIDTH-1):0] q
);

    // Declare the RAM variable
    reg [DATA_WIDTH-1:0] ram[0:2**ADDR_WIDTH-1];
    
    // Initialize the RAM with $readmemb.  Put the memory contents
    // in the file single_port_rom_init.txt.  Without this file,
    // this design will not compile.
    // See Verilog LRM 1364-2001 Section 17.2.8 for details on the
    // format of this file.

    initial
    begin
        $readmemh("ram_init.txt", ram);
    end

    // Variable to hold the registered read address
    reg [ADDR_WIDTH-1:0] addr_reg;

    always @ (posedge clk)
    begin
        // Write
        if (we)
            ram[addr] <= data;

        addr_reg <= addr;
    end

    // Continuous assignment implies read returns NEW data.
    // This is the natural behavior of the TriMatrix memory
    // blocks in Single Port mode.  
    assign q = ram[addr_reg];

endmodule

Quartus Compilation Summary

fit.summary

Fitter Status : Successful - Tue Mar 16 23:59:33 2010
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : jsim1
Top-level Entity Name : jsim1
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Final
Total logic elements : 30 / 33,216 ( < 1 % )
    Total combinational functions : 30 / 33,216 ( < 1 % )
    Dedicated logic registers : 22 / 33,216 ( < 1 % )
Total registers : 22
Total pins : 47 / 475 ( 10 % )
Total virtual pins : 0
Total memory bits : 512 / 483,840 ( < 1 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )

tan.summary

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 1.341 ns
From           : reset_n
To             : data[15]~reg0
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.061 ns
From           : single_port_ram:dev|altsyncram:ram_rtl_0|altsyncram_8ib1:auto_generated|ram_block1a0~porta_address_reg4
To             : addr[4]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -1.111 ns
From           : reset_n
To             : data[15]~reg0
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 184.23 MHz ( period = 5.428 ns )
From           : single_port_ram:dev|altsyncram:ram_rtl_0|altsyncram_8ib1:auto_generated|ram_block1a0~porta_address_reg4
To             : single_port_ram:dev|altsyncram:ram_rtl_0|altsyncram_8ib1:auto_generated|ram_block1a0~porta_address_reg0
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------