Download project files.
This is a “not-yet” working version of a pipelined RiSC-16 processor. It uses a common program/data memory. This causes a structural hazard in that the instruction fetch and data access can not occur in the same cycle.
This project does not work correctly. It is a first version of a pipelined processor. The student is invited to make the project work correctly.
The following tools have been provided.
This is Prof. Jacob's RiSC-16 assembler. It reads a program source file (.s) and generates a hex-encoded memory file suitable for use by Altera Quartus to initialize a memory unit.
Example usage:
a prog1.s prog1.txt
The pipeline simulator reads a memory file and generates an output html file. It shows two simulations, the first a single-cycle sinulation and the second a pipeline simulation. There are two versions of the program. pipe16nf does not use data-forwarding to prevent data hazards. pipe16 does use data forwarding. Both programs insert bubbles to avoid control hazards.
Example usage:
pipe16nf prog1.txt prog1.nf.html pipe16 prog1.txt prog1.pipe.html
Note that when the output of the pipeline does not match the output of the single-cycle simulation, that entry is highlighted in red.
The Quartus table viewer reads a Quartus Vector Table Output file (.tbl) and generates an html file that captures the state of the system at each positive clock pulse.
Example usage:
tblview prog1.sim.tbl view1.html
There is also a specialized version of the above program that does custom formatting of selected fields. For example, it condenses the output of the pipeline communication buffers, displays the cycle counter in decimal rather than hex, and strips the prefix (state.) from the state column.
Example usage:
jsim3view prog1.sim.tbl view2.html
Maintained by John Loomis, last updated 9 April 2010