ECE446/ECE531 Microelectronics Assignment 1

  1. The following link lists electrical test data for runs of the On Semiconductor C5 Process. I Downloaded twenty-one sets of data (run type SHR). See zip-file ( Prepare a spreadsheet with the run number (column A), the nwell sheet resistance (B), poly sheet resistance (C), N+ and P+ sheet resistance and contact resistance (columns D – G), and the poly/poly2 area capacitance (H). Calculate the mean value of each parameter. Show plots of the distribution of each value. You can work together on this problem, but specify who were the members of the work group. Generate a couple of power-point slides describing your results (for possible group presentation).

  2. An interconnect line (wire) is made from a material that has a resistivity ρ = 42 µΩ-cm. The interconnect is 140 nm thick. The line has width of 0.6 µm.
    1. Calculate the sheet resistance RS of the line.
    2. Find the line resistance if the line is 240 µm long.

  3. If the area capacitance of poly2-poly capacitors is 872 aF/(µm)2, find the thickness of the SiO2 dielectric layer between the poly and poly2 layers.

  4. Using your student number, let the fourth and fifth digits be the first two significant figures of resistance R (in kΩ) and the sixth and seventh digits be the first two significant digits of a capacitance C (in pF). Model an RC series circuit in LTSpice, using those values. Calculate the rise and fall time (from the spice simulation) and relate them to the RC time-constant. Use an ideal square-wave as a signal source, and plot the response. What period did you choose to get valid results?

  5. Set the rise/fall times of the input to the signal rise/fall times obtained is the previous exercise. Calculate the new rise and fall times of the output signal.

  6. Change the input to a sine wave in LTSpice and plot the AC response (magnitude and phase) as a function of frequency.

Maintained by John Loomis, last updated 20 January 2015