cifread
is an
object-oriented modification of a program that reads CIF files. The
Caltech Intermediate Format (CIF) is used to describe VLSI layouts.
See cif for more information.
gates1
is a work in
progress that extends the circuit classes developed earlier to handle
logic circuits. The simulator needs work!
I found several interesting examples from a book by Reese. (See WebCT excerpt)
Shown here are an application
of the STL complex class
(numeric complex
),
a function evaluator
(numeric function
),
and a string tokenizer
(string
tokenizer
).
Simple RISC system (srisc) development, level 1. (srisc1 v1). The goal of level 1 is to simulate a Nios II processor to the extent of handling arithmetic (add and subtract) and logic operations. No branching or data memory access. Version 1 is presented here - all we do is read a binary file of machine-language instructions.
netlist4 implements nodal analysis of basic electrical circuits (resistor, capacitors, inductors, and independent current and voltage sources).
bank1 is a work in progress on event-driven simulation. It explores some of the operations of a priority queue, see the event queue example.
small4.zip animates ellipical motion and provides a C++ version of the arrow class.
Horstmann chapter 2
Horstmann Violet UML Editor
Horstmann chapter 4
Horstmann chapter 5
Horstmann chapter 6
Examples 1, 2, 3, and 4 of the Graph Layout demonstration applet packages with the Java SDK.
Horstmann Graph Editor (chapter 8)
Maintained by John Loomis, last updated 2 February 2018