PIC32MX Instuction Set

The PIC32MX core execution unit implements a load/ store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The PIC32MX core contains thirty-two 32-bit general-purpose registers used for integer operations and address calculation. One additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead during interrupt/exception processing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline.

The execution unit includes:

32-bit adder used for calculating the data address
Address unit for calculating the next instruction address
Logic for branch determination and branch target address calculation
Load aligner
Bypass multiplexers used to avoid stalls when executing instructions streams where data producing instructions are followed closely by consumers of their results
Leading Zero/One detect unit for implementing the CLZ and CLO instructions
Arithmetic Logic Unit (ALU) for performing bitwise logical operations
Shifter & Store Aligner

CPU Instructions, Grouped by Function

CPU instructions are organized into the following functional groups:

Load and store
Computational
Jump and branch
Miscellaneous
Coprocessor

Each instruction is 32 bits long.

CPU Load and Store Instructions

MIPS processors use a load/store architecture; all operations are performed on operands held in processor registers and main memory is accessed only through load and store instructions.

Types of Loads and Stores

There are several different types of load and store instructions, each designed for a different purpose:

Transferring variously-sized fields (for example, LB, SW)
Trading transferred data as signed or unsigned integers (for example, LHU)
Accessing unaligned fields (for example, LWR, SWL)
Atomic memory update (read-modify-write: for instance, LL/SC)

List of CPU Load and Store Instructions

The following data sizes (as defined in the AccessLength field) are transferred by CPU load and store instructions:

Byte
Halfword
Word

Signed and unsigned integers of different sizes are supported by loads that either sign-extend or zero-extend the data loaded into the register.

Unaligned words and doublewords can be loaded or stored in just two instructions by using a pair of special instructions. For loads a LWL instruction is paired with a LWR instruction. The load instructions read the left-side or right-side bytes (left or right side of register) from an aligned word and merge them into the correct bytes of the destination register.

Loads and Stores Used for Atomic Updates

The paired instructions, Load Linked and Store Conditional, can be used to perform an atomic read-modify-write of word or doubleword cached memory locations. These instructions are used in carefully coded sequences to provide one of several synchronization primitives, including test-and-set, bit-level locks, semaphores, and sequencers and event counts.

Coprocessor Loads and Stores

If a particular coprocessor is not enabled, loads and stores to that processor cannot execute and the attempted load or store causes a Coprocessor Unusable exception. Enabling a coprocessor is a privileged operation provided by the System Control Coprocessor, CP0.

Instructions

Instruction Description Function
ADD Integer Add Rd = Rs + Rt
ADDI Integer Add Immediate Rt = Rs + Immed
ADDIU Unsigned Integer Add Immediate Rt = Rs +_U Immed
ADDIUPC Unsigned Integer Add Immediate to PC
(MIPS16e™ only) Rt = PC +_u Immed
ADDU Unsigned Integer Add Rd = Rs +_U Rt
AND Logical AND Rd = Rs & Rt
ANDI Logical AND Immediate Rt = Rs & Immed
B Unconditional Branch
(Assembler idiom for: BEQ r0, r0, offset) PC += (int)offset
BAL Branch and Link
(Assembler idiom for: BGEZAL r0, offset)
GPR[31] = PC + 8 PC += (int)offset
BEQ Branch On Equal
if Rs == Rt PC += (int)offset
BEQL Branch On Equal Likely
if Rs == Rt PC += (int)offset else Ignore Next Instruction
BGEZ Branch on Greater Than or Equal To Zero
if !Rs[31] PC += (int)offset
BGEZAL Branch on Greater Than or Equal To Zero
And Link
GPR[31] = PC + 8 if !Rs[31] PC += (int)offset
BGEZALL Branch on Greater Than or Equal To Zero
And Link Likely
GPR[31] = PC + 8 if !Rs[31] PC += (int)offset else Ignore Next Instruction
BGEZL Branch on Greater Than or Equal To Zero
Likely
if !Rs[31] PC += (int)offset else Ignore Next Instruction
BGTZ Branch on Greater Than Zero
if !Rs[31] && Rs != 0 PC += (int)offset
BGTZL Branch on Greater Than Zero Likely
if !Rs[31] && Rs != 0 PC += (int)offset else Ignore Next Instruction
BLEZ Branch on Less Than or Equal to Zero
if Rs[31] || Rs == 0 PC += (int)offset

Instruction	Description	Function
ADD	Integer Add	`Rd = Rs + Rt`
ADDI	Integer Add Immediate	`Rt = Rs + Immed`
ADDIU	Unsigned Integer Add Immediate	`Rt = Rs +_U Immed`
ADDIUPC	Unsigned Integer Add Immediate to PC (MIPS16e™ only)	`Rt = PC +_u Immed`
ADDU	Unsigned Integer Add	`Rd = Rs +_U Rt`
AND	Logical AND	`Rd = Rs & Rt`
ANDI	Logical AND Immediate	`Rt = Rs & Immed`
B	Unconditional Branch (Assembler idiom for: BEQ r0, r0, offset)	`PC += (int)offset`
BAL	Branch and Link (Assembler idiom for: BGEZAL r0, offset)	GPR[31] = PC + 8 PC += (int)offset
BEQ	Branch On Equal	if Rs == Rt PC += (int)offset
BEQL	Branch On Equal Likely	if Rs == Rt PC += (int)offset else Ignore Next Instruction
BGEZ	Branch on Greater Than or Equal To Zero	if !Rs[31] PC += (int)offset
BGEZAL	Branch on Greater Than or Equal To Zero And Link	GPR[31] = PC + 8 if !Rs[31] PC += (int)offset
BGEZALL	Branch on Greater Than or Equal To Zero And Link Likely	GPR[31] = PC + 8 if !Rs[31] PC += (int)offset else Ignore Next Instruction
BGEZL	Branch on Greater Than or Equal To Zero Likely	if !Rs[31] PC += (int)offset else Ignore Next Instruction
BGTZ	Branch on Greater Than Zero	if !Rs[31] && Rs != 0 PC += (int)offset
BGTZL	Branch on Greater Than Zero Likely	if !Rs[31] && Rs != 0 PC += (int)offset else Ignore Next Instruction
BLEZ	Branch on Less Than or Equal to Zero	if Rs[31] \|\| Rs == 0 PC += (int)offset

Instruction Description Function
BLEZ Branch on Less Than or Equal to Zero
if Rs[31] || Rs == 0 PC += (int)offset
BLEZL Branch on Less Than or Equal to Zero Likely
if Rs[31] || Rs == 0 PC += (int)offset else Ignore Next Instruction
BLTZ Branch on Less Than Zero
if Rs[31] PC += (int)offset
BLTZAL Branch on Less Than Zero And Link
GPR[31] = PC + 8 if Rs[31] PC += (int)offset
BLTZALL Branch on Less Than Zero And Link Likely
GPR[31] = PC + 8 if Rs[31] PC += (int)offset else Ignore Next Instruction
BLTZL Branch on Less Than Zero Likely
if Rs[31] PC += (int)offset else Ignore Next Instruction
BNE Branch on Not Equal
if Rs != Rt PC += (int)offset
BNEL Branch on Not Equal Likely
if Rs != Rt PC += (int)offset else Ignore Next Instruction
BREAK Breakpoint Break Exception
CLO Count Leading Ones Rd = NumLeadingOnes(Rs)
CLZ Count Leading Zeroes Rd = NumLeadingZeroes(Rs)
COP0 Coprocessor 0 Operation See Software User’s Manual
DERET Return from Debug Exception
PC = DEPC Exit Debug Mode
DI Atomically Disable Interrupts Rt = Status; StatusIE = 0
DIV Divide
LO = (int)Rs / (int)Rt HI = (int)Rs % (int)Rt
DIVU Unsigned Divide
LO = (uns)Rs / (uns)Rt HI = (uns)Rs % (uns)Rt
EHB Execution Hazard Barrier Stop instruction execution
until execution hazards are cleared
EI Atomically Enable Interrupts Rt = Status; StatusIE = 1
ERET Return from Exception
if SR[2] PC = ErrorEPC else PC = EPC SR[1] = 0 SR[2] = 0 LL = 0
EXT Extract Bit Field Rt = ExtractField(Rs, pos, size)

Instruction	Description	Function
BLEZ	Branch on Less Than or Equal to Zero	if Rs[31] \|\| Rs == 0 PC += (int)offset
BLEZL	Branch on Less Than or Equal to Zero Likely	if Rs[31] \|\| Rs == 0 PC += (int)offset else Ignore Next Instruction
BLTZ	Branch on Less Than Zero	if Rs[31] PC += (int)offset
BLTZAL	Branch on Less Than Zero And Link	GPR[31] = PC + 8 if Rs[31] PC += (int)offset
BLTZALL	Branch on Less Than Zero And Link Likely	GPR[31] = PC + 8 if Rs[31] PC += (int)offset else Ignore Next Instruction
BLTZL	Branch on Less Than Zero Likely	if Rs[31] PC += (int)offset else Ignore Next Instruction
BNE	Branch on Not Equal	if Rs != Rt PC += (int)offset
BNEL	Branch on Not Equal Likely	if Rs != Rt PC += (int)offset else Ignore Next Instruction
BREAK	Breakpoint	Break Exception
CLO	Count Leading Ones	`Rd = NumLeadingOnes(Rs)`
CLZ	Count Leading Zeroes	`Rd = NumLeadingZeroes(Rs)`
COP0	Coprocessor 0 Operation	See Software User’s Manual
DERET	Return from Debug Exception	PC = DEPC Exit Debug Mode
DI	Atomically Disable Interrupts	`Rt = Status; StatusIE = 0`
DIV	Divide	LO = (int)Rs / (int)Rt HI = (int)Rs % (int)Rt
DIVU	Unsigned Divide	LO = (uns)Rs / (uns)Rt HI = (uns)Rs % (uns)Rt
EHB	Execution Hazard Barrier	Stop instruction execution until execution hazards are cleared
EI	Atomically Enable Interrupts	`Rt = Status; StatusIE = 1`
ERET	Return from Exception	if SR[2] PC = ErrorEPC else PC = EPC SR[1] = 0 SR[2] = 0 LL = 0
EXT	Extract Bit Field	`Rt = ExtractField(Rs, pos, size)`

Instruction Description Function
INS Insert Bit Field Rt = InsertField(Rs, Rt, pos, size)
J Unconditional Jump PC = PC[31:28] | offset<<2
JAL Jump and Link
GPR[31] = PC + 8 PC = PC[31:28] | offset<<2
JALR Jump and Link Register
Rd = PC + 8 PC = Rs
JALR.HB Jump and Link Register with Hazard Barrier Like JALR, but also clears execution
and instruction hazards
JALRC Jump and Link Register Compact (MIPS16e only)
– do not execute instruction in jump delay slot
Rd = PC + 2 PC = Rs
JR Jump Register PC = Rs
JR.HB Jump Register with Hazard Barrier Like JR, but also clears execution
and instruction hazards
JRC Jump Register Compact (MIPS16e only)
– do not execute instruction in jump delay slot PC = Rs
LB Load Byte Rt = (byte)Mem[Rs+offset]
LBU Unsigned Load Byte Rt = (ubyte))Mem[Rs+offset]
LH Load Halfword Rt = (half)Mem[Rs+offset]
LHU Unsigned Load Halfword Rt = (uhalf)Mem[Rs+offset]
LL Load Linked Word
Rt = Mem[Rs+offset] LL = 1 LLAdr = Rs + offset
LUI Load Upper Immediate Rt = immediate << 16
LW Load Word Rt = Mem[Rs+offset]
LWPC Load Word, PC relative Rt = Mem[PC+offset]
LWL Load Word Left See Architecture Reference Manual
LWR Load Word Right See Architecture Reference Manual
MADD Multiply-Add HI | LO += (int)Rs * (int)Rt
MADDU Multiply-Add Unsigned HI | LO += (uns)Rs * (uns)Rt
MFC0 Move From Coprocessor 0 Rt = CPR[0, Rd, sel]
MFHI Move From HI Rd = HI
MFLO Move From LO Rd = LO
MOVN Move Conditional on Not Zero
if Rt != 0 then Rd = Rs
MOVZ Move Conditional on Zero
if Rt = 0 then Rd = Rs
MSUB Multiply-Subtract HI | LO -= (int)Rs * (int)Rt
MSUBU Multiply-Subtract Unsigned HI | LO -= (uns)Rs * (uns)Rt
MTC0 Move To Coprocessor 0 CPR[0, n, Sel] = Rt
MTHI Move To HI HI = Rs
MTLO Move To LO LO = Rs
MUL Multiply with register write
HI | LO = Unpredictable Rd = ((int)Rs * (int)Rt)31..0
MULT Integer Multiply HI | LO = (int)Rs * (int)Rd
MULTU Unsigned Multiply HI | LO = (uns)Rs * (uns)Rd

Instruction	Description	Function
INS	Insert Bit Field	`Rt = InsertField(Rs, Rt, pos, size)`
J	Unconditional Jump	`PC = PC[31:28] \| offset<<2`
JAL	Jump and Link	GPR[31] = PC + 8 PC = PC[31:28] \| offset<<2
JALR	Jump and Link Register	Rd = PC + 8 PC = Rs
JALR.HB	Jump and Link Register with Hazard Barrier	Like JALR, but also clears execution and instruction hazards
JALRC	Jump and Link Register Compact (MIPS16e only) – do not execute instruction in jump delay slot	Rd = PC + 2 PC = Rs
JR	Jump Register	`PC = Rs`
JR.HB	Jump Register with Hazard Barrier	Like JR, but also clears execution and instruction hazards
JRC	Jump Register Compact (MIPS16e only) – do not execute instruction in jump delay slot	`PC = Rs`
LB	Load Byte	`Rt = (byte)Mem[Rs+offset]`
LBU	Unsigned Load Byte	`Rt = (ubyte))Mem[Rs+offset]`
LH	Load Halfword	`Rt = (half)Mem[Rs+offset]`
LHU	Unsigned Load Halfword	`Rt = (uhalf)Mem[Rs+offset]`
LL	Load Linked Word	Rt = Mem[Rs+offset] LL = 1 LLAdr = Rs + offset
LUI	Load Upper Immediate	`Rt = immediate << 16`
LW	Load Word	`Rt = Mem[Rs+offset]`
LWPC	Load Word, PC relative	`Rt = Mem[PC+offset]`
LWL	Load Word Left	See Architecture Reference Manual
LWR	Load Word Right	See Architecture Reference Manual
MADD	Multiply-Add	`HI \| LO += (int)Rs * (int)Rt`
MADDU	Multiply-Add Unsigned	`HI \| LO += (uns)Rs * (uns)Rt`
MFC0	Move From Coprocessor 0	`Rt = CPR[0, Rd, sel]`
MFHI	Move From HI	`Rd = HI`
MFLO	Move From LO	`Rd = LO`
MOVN	Move Conditional on Not Zero	if Rt != 0 then Rd = Rs
MOVZ	Move Conditional on Zero	if Rt = 0 then Rd = Rs
MSUB	Multiply-Subtract	`HI \| LO -= (int)Rs * (int)Rt`
MSUBU	Multiply-Subtract Unsigned	`HI \| LO -= (uns)Rs * (uns)Rt`
MTC0	Move To Coprocessor 0	`CPR[0, n, Sel] = Rt`
MTHI	Move To HI	`HI = Rs`
MTLO	Move To LO	`LO = Rs`
MUL	Multiply with register write	HI \| LO = Unpredictable Rd = ((int)Rs * (int)Rt)31..0
MULT	Integer Multiply	`HI \| LO = (int)Rs * (int)Rd`
MULTU	Unsigned Multiply	`HI \| LO = (uns)Rs * (uns)Rd`

Instruction Description Function
NOP No Operation Assembler idiom for:
SLL r0, r0, r0
NOR Logical NOR Rd = ~(Rs | Rt)
OR Logical OR Rd = Rs | Rt
ORI Logical OR Immediate Rt = Rs | Immed
RDHWR Read Hardware Register Allows unprivileged access to
registers enabled by HWREna register
RDPGPR Read GPR from Previous Shadow Set Rt = SGPR[SRSCtlPSS, Rd]
RESTORE Restore registers and deallocate stack frame
(MIPS16e™ only) See Architecture Reference Manual
ROTR Rotate Word Right Rd = Rt[sa-1:0] | Rt[31:sa]
ROTRV Rotate Word Right Variable Rd = Rt[Rs-1:0] | Rt[31:Rs]
SAVE Save registers and allocate stack frame
(MIPS16e only) See Architecture Reference Manual
SB Store Byte (byte)Mem[Rs+offset] = Rt
SC Store Conditional Word
if LL = 1 mem[Rs+offset] = Rt Rt = LL
SDBBP Software Debug Break Point Trap to SW Debug Handler
SEB Sign-Extend Byte Rd = (byte)Rs
SEH Sign-Extend Half Rd = (half)Rs
SH Store Half (half)Mem[Rs+offset] = Rt
SLL Shift Left Logical Rd = Rt << sa
SLLV Shift Left Logical Variable Rd = Rt << Rs[4:0]
SLT Set on Less Than
if (int)Rs < (int)Rt Rd = 1 else Rd = 0
SLTI Set on Less Than Immediate
if (int)Rs < (int)Immed Rt = 1 else Rt = 0
SLTIU Set on Less Than Immediate Unsigned
if (uns)Rs < (uns)Immed Rt = 1 else Rt = 0
SLTU Set on Less Than Unsigned
if (uns)Rs < (uns)Immed Rd = 1 else Rd = 0
SRA Shift Right Arithmetic Rd = (int)Rt >> sa
SRAV Shift Right Arithmetic Variable Rd = (int)Rt >> Rs[4:0]
SRL Shift Right Logical Rd = (uns)Rt >> sa
SRLV Shift Right Logical Variable Rd = (uns)Rt >> Rs[4:0]
SSNOP Superscalar Inhibit No Operation NOP
SUB Integer Subtract Rt = (int)Rs - (int)Rd
SUBU Unsigned Subtract Rt = (uns)Rs - (uns)Rd
SW Store Word Mem[Rs+offset] = Rt
SWL Store Word Left See Architecture Reference Manual

Instruction	Description	Function
NOP	No Operation	Assembler idiom for: `SLL r0, r0, r0`
NOR	Logical NOR	`Rd = ~(Rs \| Rt)`
OR	Logical OR	`Rd = Rs \| Rt`
ORI	Logical OR Immediate	`Rt = Rs \| Immed`
RDHWR	Read Hardware Register	Allows unprivileged access to registers enabled by HWREna register
RDPGPR	Read GPR from Previous Shadow Set	`Rt = SGPR[SRSCtlPSS, Rd]`
RESTORE	Restore registers and deallocate stack frame (MIPS16e™ only)	See Architecture Reference Manual
ROTR	Rotate Word Right	`Rd = Rt[sa-1:0] \| Rt[31:sa]`
ROTRV	Rotate Word Right Variable	`Rd = Rt[Rs-1:0] \| Rt[31:Rs]`
SAVE	Save registers and allocate stack frame (MIPS16e only)	See Architecture Reference Manual
SB	Store Byte	`(byte)Mem[Rs+offset] = Rt`
SC	Store Conditional Word	if LL = 1 mem[Rs+offset] = Rt Rt = LL
SDBBP	Software Debug Break Point	Trap to SW Debug Handler
SEB	Sign-Extend Byte	`Rd = (byte)Rs`
SEH	Sign-Extend Half	`Rd = (half)Rs`
SH	Store Half	`(half)Mem[Rs+offset] = Rt`
SLL	Shift Left Logical	`Rd = Rt << sa`
SLLV	Shift Left Logical Variable	`Rd = Rt << Rs[4:0]`
SLT	Set on Less Than	if (int)Rs < (int)Rt Rd = 1 else Rd = 0
SLTI	Set on Less Than Immediate	if (int)Rs < (int)Immed Rt = 1 else Rt = 0
SLTIU	Set on Less Than Immediate Unsigned	if (uns)Rs < (uns)Immed Rt = 1 else Rt = 0
SLTU	Set on Less Than Unsigned	if (uns)Rs < (uns)Immed Rd = 1 else Rd = 0
SRA	Shift Right Arithmetic	`Rd = (int)Rt >> sa`
SRAV	Shift Right Arithmetic Variable	`Rd = (int)Rt >> Rs[4:0]`
SRL	Shift Right Logical	`Rd = (uns)Rt >> sa`
SRLV	Shift Right Logical Variable	`Rd = (uns)Rt >> Rs[4:0]`
SSNOP	Superscalar Inhibit No Operation	NOP
SUB	Integer Subtract	`Rt = (int)Rs - (int)Rd`
SUBU	Unsigned Subtract	`Rt = (uns)Rs - (uns)Rd`
SW	Store Word	`Mem[Rs+offset] = Rt`
SWL	Store Word Left	See Architecture Reference Manual

Instruction Description Function
SWR Store Word Right See Architecture Reference Manual
SYNC Synchronize See Software User’s Manual
SYSCALL System Call SystemCallException
TEQ Trap if Equal
if Rs == Rt TrapException
TEQI Trap if Equal Immediate
if Rs == (int)Immed TrapException
TGE Trap if Greater Than or Equal
if (int)Rs >= (int)Rt TrapException
TGEI Trap if Greater Than or Equal Immediate
if (int)Rs >= (int)Immed TrapException
TGEIU Trap if Greater Than or Equal Immediate Unsigned
if (uns)Rs >= (uns)Immed TrapException
TGEU Trap if Greater Than or Equal Unsigned
if (uns)Rs >= (uns)Rt TrapException
TLT Trap if Less Than
if (int)Rs < (int)Rt TrapException
TLTI Trap if Less Than Immediate
if (int)Rs < (int)Immed TrapException
TLTIU Trap if Less Than Immediate Unsigned
if (uns)Rs < (uns)Immed TrapException
TLTU Trap if Less Than Unsigned
if (uns)Rs < (uns)Rt TrapException
TNE Trap if Not Equal
if Rs != Rt TrapException
TNEI Trap if Not Equal Immediate
if Rs != (int)Immed TrapException
WAIT Wait for Interrupts Stall until interrupt occurs
WRPGPR Write to GPR in Previous Shadow Set SGPR[SRSCtlPSS, Rd] = Rt
WSBH Word Swap Bytes Within Halfwords Rd = Rt[23:16] | Rt[31:24] ... | Rt[7:0] | Rt[15:8]
XOR Exclusive OR Rd = Rs ^ Rt
XORI Exclusive OR Immediate Rt = Rs ^ (uns)Immed
ZEB Zero-extend byte (MIPS16e™ only) Rt = (ubyte) Rs
ZEH Zero-extend half (MIPS16e only) Rt = (uhalf) Rs

Instruction	Description	Function
SWR	Store Word Right	See Architecture Reference Manual
SYNC	Synchronize	See Software User’s Manual
SYSCALL	System Call	SystemCallException
TEQ	Trap if Equal	if Rs == Rt TrapException
TEQI	Trap if Equal Immediate	if Rs == (int)Immed TrapException
TGE	Trap if Greater Than or Equal	if (int)Rs >= (int)Rt TrapException
TGEI	Trap if Greater Than or Equal Immediate	if (int)Rs >= (int)Immed TrapException
TGEIU	Trap if Greater Than or Equal Immediate Unsigned	if (uns)Rs >= (uns)Immed TrapException
TGEU	Trap if Greater Than or Equal Unsigned	if (uns)Rs >= (uns)Rt TrapException
TLT	Trap if Less Than	if (int)Rs < (int)Rt TrapException
TLTI	Trap if Less Than Immediate	if (int)Rs < (int)Immed TrapException
TLTIU	Trap if Less Than Immediate Unsigned	if (uns)Rs < (uns)Immed TrapException
TLTU	Trap if Less Than Unsigned	if (uns)Rs < (uns)Rt TrapException
TNE	Trap if Not Equal	if Rs != Rt TrapException
TNEI	Trap if Not Equal Immediate	if Rs != (int)Immed TrapException
WAIT	Wait for Interrupts	Stall until interrupt occurs
WRPGPR	Write to GPR in Previous Shadow Set	`SGPR[SRSCtlPSS, Rd] = Rt`
WSBH	Word Swap Bytes Within Halfwords	`Rd = Rt[23:16] \| Rt[31:24] ... \| Rt[7:0] \| Rt[15:8]`
XOR	Exclusive OR	`Rd = Rs ^ Rt`
XORI	Exclusive OR Immediate	`Rt = Rs ^ (uns)Immed`
ZEB	Zero-extend byte (MIPS16e™ only)	`Rt = (ubyte) Rs`
ZEH	Zero-extend half (MIPS16e only)	`Rt = (uhalf) Rs`

Maintained by John Loomis, last updated 28 July 2008