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srisc3.v
module srisc3(input clock, input reset, output reg [7:0] pc, output [31:0] ir, output [31:0] results);
// instantiate memory
wire [7:0] next_pc;
inst inst_cache(
.address(next_pc),
.clock(clock),
.q(ir)
);
assign next_pc = pc + 1'b1;
always @(posedge clock or negedge reset)
if (!reset)
pc <= 8'hff; // so that next_pc starts at zero
else
pc <= next_pc;
// Instantiate register file
wire [31:0] da, db, dc;
wire [4:0] ra, rb, rc;
wire write_enable;
reg_file regs(
.clock(clock),
.reset(reset),
.da(da),
.db(db),
.dc(dc),
.ra(ra),
.rb(rb),
.rc(rc),
.write_enable(write_enable)
);
// decode instruction
wire [5:0] op, opx;
wire [31:0] immedse;
wire [4:0] shf;
assign op = ir[5:0];
assign ra = ir[31:27];
assign rb = ir[26:22];
assign opx = ir[16:11];
assign shf = ir[10:6];
assign immedse = {(ir[21]?16'hffff:16'h0000),ir[21:6]};
wire iflag;
assign iflag = (op!=6'h3a);
assign rc = (iflag? rb: ir[21:17]);
//--------------------------------------------------------
// instantiate r-format control unit
wire [2:0] rcontrol;
rformat unit1(
.opx(opx),
.control(rcontrol)
);
// instantiate i-format control unit
wire [2:0] icontrol;
wire [1:0] muxc;
iformat unit2(
.op(op),
.control(icontrol),
.muxc(muxc)
);
//----------------------------------------------------------
// instantiate immediate/b-data multiplexer
wire [31:0] dmuxi; // muxi output
wire [1:0] muxi_control = (iflag? muxc: 2'b00);
muxi mux1(
.dst(dmuxi),
.b(db),
.immedse(immedse),
.control(muxi_control)
);
//----------------------------------------------------------
// instantiate ALU
wire [31:0] dalu; // alu output
wire [2:0] alu_control = (iflag? icontrol: rcontrol);
wire zero, ovfl;
alu my_alu(
.a(da),
.b(dmuxi),
.control(alu_control),
.c(dalu),
.zero(zero),
.ovfl(ovfl)
);
//----------------------------------------------------------
// send the output of the ALU back to the register file
assign dc = dalu;
assign write_enable = 1'b1;
assign results = dc; // also send output outside the module for display
endmodule
iformat.v
module iformat(op,control,muxc);
input [5:0] op;
output [2:0] control;
output [1:0] muxc;
reg [2:0] control;
reg [1:0] muxc;
always
case (op)
6'h04:
begin
control <= 3'b000; // addi
muxc <= 2'b01; // se
end
6'h0c:
begin
control <= 3'b100; // andi
muxc <= 2'b10;
end
6'h14:
begin
control <= 3'b101; // ori
muxc <= 2'b10;
end
6'h1c:
begin
control <= 3'b110; // xori
muxc <= 2'b10;
end
6'h2c:
begin
control <= 3'b100; // andhi
muxc <= 2'b11; // hi
end
6'h34:
begin
control <= 3'b101; // orhi
muxc <= 2'b11; // hi
end
6'h3c:
begin
control <= 3'b110; // xorhi
muxc <= 2'b11; // hi
end
default:
begin
control <= 3'b000;
muxc <= 2'b00; // nop
end
endcase
endmodule
inst.v
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: inst.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 175 11/20/2007 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module inst (
address,
clock,
q);
input [7:0] address;
input clock;
output [31:0] q;
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "isa1.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "isa1.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "isa1.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
muxi.v
/*
* control:
* 00 b
* 01 immedse, (immed sign-extended)
* 10 {16'h0000, immed} (not sign-extended)
* 11 {immed, 16'h0000}
*/
module muxi(dst,b,immedse,control);
parameter BITS = 32;
input [BITS-1:0] b, immedse;
input [1:0] control;
output [BITS-1:0] dst;
reg [BITS-1:0] dst;
always
case (control)
2'b00: dst = b;
2'b01: dst = immedse;
2'b10: dst = {16'h0000, immedse[15:0]};
2'b11: dst = {immedse[15:0],16'h0000};
endcase
endmodule
reg_file.v
module reg_file(clock,reset,da,db,dc,ra,rb,rc,write_enable);
parameter BITS = 32;
input [BITS-1:0] dc;
output [BITS-1:0] da,db;
input [4:0] ra,rb,rc;
input clock, write_enable, reset;
reg [BITS-1:0] r[1:31];
integer i;
always @(posedge clock or negedge reset)
begin
if (!reset)
for (i=1; i<32; i=i+1) r[i] = 0;
else if (write_enable && rc) r[rc] = dc;
end
assign da = (ra? r[ra]: 0);
assign db = (rb? r[rb]: 0);
endmodule
rformat.v
module rformat(opx,control);
input [5:0] opx;
output [2:0] control;
reg [2:0] control;
always
case (opx)
6'h06: control = 3'b111; // nor
6'h0e: control = 3'b100; // and
6'h16: control = 3'b101; // or
6'h1e: control = 3'b110; // xor
6'h31: control = 3'b000; // add
6'h39: control = 3'b001; // sub
default: control = 3'b000;
endcase
endmodule
alu.v
/*
* control:
* 000 add, signed
* 001 subtract, signed
* 010 add, unsigned
* 011 subtract, unsigned
* --------------------------------------------
* 100 AND
* 101 OR
* 110 XOR
* 111 NOR
*/
module alu(a,b,control,c,zero,neg,ovfl);
parameter BITS = 32;
input [BITS-1:0] a, b;
input [2:0] control;
output [BITS-1:0] c;
output zero, neg, ovfl;
wire subtract;
assign subtract = control[0];
// add-subtract unit
wire [BITS-1:0] sum;
wire [BITS-1:0] bn;
wire cin, cout;
assign cin = subtract;
assign bn = (subtract? ~b: b);
assign {cout, sum} = a+bn+cin;
// logic unit
reg [BITS-1:0] out;
always
case (control[1:0])
2'b00: out = a&b;
2'b01: out = a|b;
2'b10: out = a^b;
2'b11: out = ~(a|b);
endcase
wire zero, sgn, unsgn;
assign zero = ~(|sum);
assign sgn = (sum[BITS-1]? (~a[BITS-1])&(~bn[BITS-1]): a[BITS-1]&bn[BITS-1] );
assign unsgn = cout^subtract;
assign ovfl = (control[1]? unsgn: sgn);
assign neg = (control[1]? unsgn: sum[BITS-1]);
assign c = (control[2]? out: sum);
endmodule
fit.summary
Fitter Status : Successful - Fri Feb 15 10:29:22 2008
Quartus II Version : 7.2 Build 175 11/20/2007 SP 1 SJ Web Edition
Revision Name : srisc3
Top-level Entity Name : srisc3
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Final
Total logic elements : 1,593 / 33,216 ( 5 % )
Total combinational functions : 1,592 / 33,216 ( 5 % )
Dedicated logic registers : 1,000 / 33,216 ( 3 % )
Total registers : 1000
Total pins : 74 / 475 ( 16 % )
Total virtual pins : 0
Total memory bits : 8,192 / 483,840 ( 2 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )
tan.summary-------------------------------------------------------------------------------------- Timing Analyzer Summary -------------------------------------------------------------------------------------- Type : Worst-case tco Slack : N/A Required Time : None Actual Time : 23.758 ns From : inst:inst_cache|altsyncram:altsyncram_component|altsyncram_6j71:auto_generated|ram_block1a18~porta_address_reg7 To : results[26] From Clock : clock To Clock : -- Failed Paths : 0 Type : Clock Setup: 'clock' Slack : N/A Required Time : None Actual Time : 54.64 MHz ( period = 18.302 ns ) From : inst:inst_cache|altsyncram:altsyncram_component|altsyncram_6j71:auto_generated|ram_block1a18~porta_address_reg7 To : reg_file:regs|r[20][27] From Clock : clock To Clock : clock Failed Paths : 0 Type : Total number of failed paths Slack : Required Time : Actual Time : From : To : From Clock : To Clock : Failed Paths : 0 --------------------------------------------------------------------------------------
Maintained by John Loomis, last updated Sun Mar 09 16:45:40 2008