SRISC3 CPU

ALU Instructions

operation	R-format	I-format
add	`add`	`addi`
subtract	`sub`	`subi`
AND	`and`	`andi`	`andhi`
OR	`or`	`ori`	`orhi`
XOR	`xor`	`xori`	`xorhi`
NOR	`nor`

pseudo-instruction

addi rB ← rA + se(immed)

Immediate logic operations use zero extension, not sign extension for the immediate operand.

Datapath

ALU Operations

control	operation
000	add, signed
001	subtract, signed
010	add, unsigned
011	subtract, unsigned
100	AND
101	OR
110	XOR
111	NOR

Input Multiplexer

mux	operation
00	`db` (from register file)
01	`immedse` (sign-extended)
10	`{zero,immedse[15:0]}`
11	`{immedse[15:0],zero}`

Opcode Decoding Maps


wire [1:0] muxi_control = (iflag? muxc: 2'b00);
wire [2:0] alu_control = (iflag? icontrol: rcontrol);

I-Format

R-Format

type op mux ictl
addi 0x04 01 000
andi 0x0c 10 100
ori 0x14 10 101
xori 0x1c 10 110
andhi 0x2e 11 100
orhi 0x34 11 101
xorhi 0x3c 11 110

type opx rctl
nor 0x06 111
and 0x0e 100
or 0x16 101
xor 0x1e 110
add 0x31 000
sub 0x39 001

Maintained by John Loomis, last updated 22 October 2008