srisc5.v
module srisc5(input clock, input reset, output reg [7:0] pc, output [31:0] ir, output [31:0] results);
// instantiate memory
wire [7:0] next_pc;
inst inst_cache(
.address(next_pc),
.clock(clock),
.q(ir)
);
assign next_pc = pc + 1'b1;
always @(posedge clock or negedge reset)
if (!reset)
pc <= 8'hff; // so that next_pc starts at zero
else
pc <= next_pc;
// Instantiate register file
wire [31:0] da, db;
reg [31:0] dc;
wire [4:0] ra, rb, rc;
wire write_enable;
reg_file regs(
.clock(clock),
.reset(reset),
.da(da),
.db(db),
.dc(dc),
.ra(ra),
.rb(rb),
.rc(rc),
.write_enable(write_enable)
);
// decode instruction
wire [5:0] op, opx;
wire [31:0] immedse;
wire [4:0] shf;
assign op = ir[5:0];
assign ra = ir[31:27];
assign rb = ir[26:22];
assign opx = ir[16:11];
assign shf = ir[10:6];
assign immedse = {(ir[21]?16'hffff:16'h0000),ir[21:6]};
wire iflag;
assign iflag = (op!=6'h3a);
assign rc = (iflag? rb: ir[21:17]);
//--------------------------------------------------------
// instantiate r-format control unit
wire [5:0] rcontrol;
rformat unit1(
.opx(opx),
.control(rcontrol)
);
// instantiate i-format control unit
wire [5:0] icontrol;
wire [1:0] muxc;
iformat unit2(
.op(op),
.control(icontrol),
.muxc(muxc)
);
wire [5:0] control = (iflag? icontrol: rcontrol);
//----------------------------------------------------------
// instantiate immediate/b-data multiplexer
wire [31:0] dmuxi; // muxi output
wire [1:0] muxi_control = (iflag? muxc: 2'b00);
muxi mux1(
.dst(dmuxi),
.b(db),
.immedse(immedse),
.control(muxi_control)
);
//----------------------------------------------------------
// instantiate ALU
wire [31:0] dc1; // alu output
wire [2:0] alu_control = (control[4:3]==(2'b01)? {1'b0,control[2],1'b1}: control[2:0]);
wire zero, neg, ovfl;
alu my_alu(
.a(da),
.b(dmuxi),
.control(alu_control),
.c(dc1),
.zero(zero),
.neg(neg),
.ovfl(ovfl)
);
//----------------------------------------------------------
// instantiate barrel shifter
wire [4:0] shift = (control[3]? shf: db[4:0]);
wire [31:0] dc2;
barrel brl(
.inp(da),
.control(control[2:0]),
.shift(shift),
.out(dc2)
);
//----------------------------------------------------------
// include logic for compare operations
wire cmp = (control[1]? neg: zero)^control[0];
//----------------------------------------------------------
// instantiate dc-bus multiplexer
wire [2:0] muxd = control[5:3];
always
case(muxd[1:0])
2'b00: dc <= dc1;
2'b01: dc <= {31'h00000000,cmp};
2'b10: dc <= dc2;
2'b11: dc <= dc2;
default: dc <= 32'h00000000;
endcase
assign write_enable = 1'b1;
assign results = dc; // also send output outside the module for display
endmodule
barrel.v
/*
* control
* 000 sll shift left logical
* 001 srl shift right logical
* 011 sra shift right arithmetic
* 100 rol rotate left
* 101 ror rotate right
*/
module barrel(inp,control,shift,out);
input [31:0] inp;
input [2:0] control;
input [4:0] shift;
output [31:0] out;
reg [31:0] bit4,bit3,bit2,bit1,out;
parameter sll = 3'b000,
srl = 3'b001,
sra = 3'b011,
rol = 3'b100,
ror = 3'b101;
// bit 4 (16)
always
if (shift[4])
case (control)
sll: bit4 = {inp[15:0],16'h0000};
srl: bit4 = {16'h0000,inp[31:16]};
sra: bit4 = {(inp[31]? 16'hFFFF: 16'h0000),inp[31:16]};
rol: bit4 = {inp[15:0],inp[31:16]};
ror: bit4 = {inp[15:0],inp[31:16]};
default: bit4 = inp;
endcase
else bit4=inp;
// bit 3 (8)
always
if (shift[3])
case (control)
sll: bit3 = {bit4[23:0],8'h00};
srl: bit3 = {8'h00,bit4[31:8]};
sra: bit3 = {(bit4[31]? 8'hFF: 8'h00),bit4[31:8]};
rol: bit3 = {bit4[23:0],bit4[31:24]};
ror: bit3 = {bit4[7:0],bit4[31:8]};
default: bit3 = bit4;
endcase
else bit3 = bit4;
// bit 2 (4)
always
if (shift[2])
case (control)
sll: bit2 = {bit3[27:0],4'h0};
srl: bit2 = {4'h0,bit3[31:4]};
sra: bit2 = {(bit3[31]? 4'hf: 4'h0),bit3[31:4]};
rol: bit2 = { bit3[27:0],bit3[31:28]};
ror: bit2 = { bit3[3:0],bit3[31:4]};
default: bit2 = bit3;
endcase
else bit2 = bit3;
// bit 1 (2)
always
if (shift[1])
case (control)
sll: bit1 = {bit2[29:0],2'b00};
srl: bit1 = {2'b00,bit2[31:2]};
sra: bit1 = {(bit2[31]? 2'b11: 2'b00),bit2[31:2]};
rol: bit1 = {bit2[29:0],bit2[31:30]};
ror: bit1 = {bit2[1:0],bit2[31:2]};
default: bit1 = bit2;
endcase
else bit1 = bit2;
// bit 0 (1)
always
if (shift[0])
case (control)
sll: out = {bit1[30:0],1'b0};
srl: out = {1'b0,bit1[31:1]};
sra: out = {bit1[31],bit1[31:1]};
rol: out = {bit1[30:0],bit1[31]};
ror: out = {bit1[0],bit1[31:1]};
default: out = bit1;
endcase
else out = bit1;
endmodule
iformat.v
module iformat(op,control,muxc,branch);
input [5:0] op;
output [5:0] control;
output [1:0] muxc;
output branch;
reg [5:0] control;
reg [1:0] muxc;
always
case (op)
6'h00: // call
begin
control <= 6'h28;
muxc <= 2'b00;
end
6'h04:
begin
control <= 6'h00; // addi
muxc <= 2'b01; // se
end
6'h06: // br
begin
control <= 6'h08;
muxc <= 2'b00;
end
6'h08:
begin
control <= 6'h0b; // cmpgei
muxc <= 2'b01;
end
6'h0c:
begin
control <= 6'h04; // andi
muxc <= 2'b10;
end
6'h0e: // bge
begin
control <= 6'h0b;
muxc <= 2'b00;
end
6'h10:
begin
control <= 6'h0a; // cmplti
muxc <= 2'b01;
end
6'h14:
begin
control <= 6'h05; // ori
muxc <= 2'b10;
end
6'h16: // blt
begin
control <= 6'h0a;
muxc <= 2'b00;
end
6'h18:
begin
control <= 6'h09; // cmpnei
muxc <= 2'b01;
end
6'h1c:
begin
control <= 6'h06; // xori
muxc <= 2'b10;
end
6'h1e:
begin
control <= 6'h09; // bne
muxc <= 2'b00;
end
6'h20:
begin
control <= 6'h08; // cmpeqi
muxc <= 2'b01;
end
6'h26:
begin
control <= 6'h08; // beq
muxc <= 2'b00;
end
6'h28:
begin
control <= 6'h0f; // cmpgeui
muxc <= 2'b01;
end
6'h2c:
begin
control <= 6'h04; // andhi
muxc <= 2'b11; // hi
end
6'h2e:
begin
control <= 6'h0f; // bgeu
muxc <= 2'b00;
end
6'h30:
begin
control <= 6'h0e; // cmpltu
muxc <= 2'b01;
end
6'h34:
begin
control <= 6'h05; // orhi
muxc <= 2'b11; // hi
end
6'h36:
begin
control <= 6'h0e; // bltu
muxc <= 2'b00;
end
6'h3c:
begin
control <= 6'h06; // xorhi
muxc <= 2'b11; // hi
end
default:
begin
control <= 6'h00;
muxc <= 2'b00; // nop
end
endcase
assign branch = (control[5:3]==3'b001)&(!muxc[0]);
endmodule
inst.v
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: inst.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 175 11/20/2007 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module inst (
address,
clock,
q);
input [7:0] address;
input clock;
output [31:0] q;
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "isa3.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "isa3.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "isa1.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL inst_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
muxi.v
/*
* control:
* 00 b
* 01 immedse, (immed sign-extended)
* 10 {16'h0000, immed} (not sign-extended)
* 11 {immed, 16'h0000}
*/
module muxi(dst,b,immedse,control);
parameter BITS = 32;
input [BITS-1:0] b, immedse;
input [1:0] control;
output [BITS-1:0] dst;
reg [BITS-1:0] dst;
always
case (control)
2'b00: dst = b;
2'b01: dst = immedse;
2'b10: dst = {16'h0000, immedse[15:0]};
2'b11: dst = {immedse[15:0],16'h0000};
endcase
endmodule
reg_file.v
module reg_file(clock,reset,da,db,dc,ra,rb,rc,write_enable);
parameter BITS = 32;
input [BITS-1:0] dc;
output [BITS-1:0] da,db;
input [4:0] ra,rb,rc;
input clock, write_enable, reset;
reg [BITS-1:0] r[1:31];
integer i;
always @(posedge clock or negedge reset)
begin
if (!reset)
for (i=1; i<32; i=i+1) r[i] = 0;
else if (write_enable && rc) r[rc] = dc;
end
assign da = (ra? r[ra]: 0);
assign db = (rb? r[rb]: 0);
endmodule
rformat.v
/*
* control[5:3] control[2:0]
* 000 alu operation 000 add (signed) sll
* 001 compare 001 subtract (signed) srl
* 010 shift 010 add (unsigned)
* 011 shift immediate 011 subtract (unsigned) sra
* 100 and rol
* control[1:0] 101 or ror
* 00 == 110 xor
* 01 != 111 nor
* 10 <
* 11 >=
* control[2] control[5:3]
* 0 signed 100 load data
* 1 unsigned 101 nextpc
* 110 nop, jr (jmp, ret)
* 111 nextpc, jr (callr)
*/
module rformat(opx,control);
input [5:0] opx;
output [5:0] control;
reg [5:0] control;
always
case (opx)
6'h02: control = 6'h1c; // roli
6'h03: control = 6'h14; // rol
6'h05: control = 6'h30; // ret
6'h06: control = 6'h07; // nor
6'h08: control = 6'h0b; // cmpge
6'h0b: control = 6'h15; // ror
6'h0d: control = 6'h30; // jmp
6'h0e: control = 6'h04; // and
6'h10: control = 6'h0a; // cmplt
6'h12: control = 6'h18; // slli
6'h13: control = 6'h10; // sll
6'h16: control = 6'h05; // or
6'h18: control = 6'h09; // cmpne
6'h1a: control = 6'h19; // srli
6'h1b: control = 6'h11; // srl
6'h1c: control = 6'h28; // nextpc
6'h1d: control = 6'h38; // callr
6'h1e: control = 6'h06; // xor
6'h20: control = 6'h08; // cmpeq
6'h28: control = 6'h0f; // cmpgeu
6'h30: control = 6'h0e; // cmpltu
6'h31: control = 6'h00; // add
6'h39: control = 6'h01; // sub
6'h3a: control = 6'h1b; // srai
6'h3b: control = 6'h13; // sra
default: control = 6'h00;
endcase
endmodule
alu.v
/*
* control:
* 000 add, signed
* 001 subtract, signed
* 010 add, unsigned
* 011 subtract, unsigned
* --------------------------------------------
* 100 AND
* 101 OR
* 110 XOR
* 111 NOR
*/
module alu(a,b,control,c,zero,neg,ovfl);
parameter BITS = 32;
input [BITS-1:0] a, b;
input [2:0] control;
output [BITS-1:0] c;
output zero, neg, ovfl;
wire subtract;
assign subtract = control[0];
// add-subtract unit
wire [BITS-1:0] sum;
wire [BITS-1:0] bn;
wire cin, cout;
assign cin = subtract;
assign bn = (subtract? ~b: b);
assign {cout, sum} = a+bn+cin;
// logic unit
reg [BITS-1:0] out;
always
case (control[1:0])
2'b00: out = a&b;
2'b01: out = a|b;
2'b10: out = a^b;
2'b11: out = ~(a|b);
endcase
wire zero, sgn, unsgn;
assign zero = ~(|sum);
assign sgn = (sum[BITS-1]? (~a[BITS-1])&(~bn[BITS-1]): a[BITS-1]&bn[BITS-1] );
assign unsgn = cout^subtract;
assign ovfl = (control[1]? unsgn: sgn);
assign neg = (control[1]? unsgn: sum[BITS-1]);
assign c = (control[2]? out: sum);
endmodule
fit.summary
Fitter Status : Successful - Fri Feb 15 16:04:04 2008
Quartus II Version : 7.2 Build 175 11/20/2007 SP 1 SJ Web Edition
Revision Name : srisc5
Top-level Entity Name : srisc5
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Final
Total logic elements : 2,069 / 33,216 ( 6 % )
Total combinational functions : 2,047 / 33,216 ( 6 % )
Dedicated logic registers : 1,000 / 33,216 ( 3 % )
Total registers : 1000
Total pins : 74 / 475 ( 16 % )
Total virtual pins : 0
Total memory bits : 8,192 / 483,840 ( 2 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )
tan.summary-------------------------------------------------------------------------------------- Timing Analyzer Summary -------------------------------------------------------------------------------------- Type : Worst-case tco Slack : N/A Required Time : None Actual Time : 30.067 ns From : inst:inst_cache|altsyncram:altsyncram_component|altsyncram_8j71:auto_generated|ram_block1a18~porta_address_reg7 To : results[28] From Clock : clock To Clock : -- Failed Paths : 0 Type : Clock Setup: 'clock' Slack : N/A Required Time : None Actual Time : 41.26 MHz ( period = 24.239 ns ) From : inst:inst_cache|altsyncram:altsyncram_component|altsyncram_8j71:auto_generated|ram_block1a18~porta_address_reg7 To : reg_file:regs|r[24][27] From Clock : clock To Clock : clock Failed Paths : 0 Type : Total number of failed paths Slack : Required Time : Actual Time : From : To : From Clock : To Clock : Failed Paths : 0 --------------------------------------------------------------------------------------
Maintained by John Loomis, last updated Fri Feb 15 16:08:43 2008