Download: rs232lab.zip
These files are from the University Program IP core on the RS232 interface for Nios II.
The FIFO is implemented via an LPM. I used the "megawizard" to configure a similar (I think) unit. The wizard generated a set of waveforms for the FIFO. It also referenced a pdf document on the fifo.
The top-level module does nothing yet.
rs232lab.v
module rs232lab( // Clock Input (50 MHz) input CLOCK_50, // Push Buttons input [3:0] KEY, // DPDT Switches input [17:0] SW, // 7-SEG Displays output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, // LEDs output [8:0] LEDG, // LED Green[8:0] output [17:0] LEDR, // LED Red[17:0] // GPIO Connections inout [35:0] GPIO_0, GPIO_1 ); // set all inout ports to tri-state assign GPIO_0 = 36'hzzzzzzzzz; assign GPIO_1 = 36'hzzzzzzzzz; wire RST; assign RST = KEY[0]; // Assign green LEDs assign LEDG[8:0] = 0; // Connect dip switches to red LEDS assign LEDR[17:0] = SW[17:0]; // blank remaining digits wire [6:0] blank = 7'b111_1111; assign HEX0 = blank; assign HEX1 = blank; assign HEX2 = blank; assign HEX3 = blank; assign HEX4 = blank; assign HEX5 = blank; assign HEX6 = blank; assign HEX7 = blank; endmodule
Altera_UP_Avalon_RS232.v
/***************************************************************************** * * * Module: Altera_UP_Avalon_RS232 * * Description: * * This module reads and writes data to the RS232 connectpr on Altera's * * DE1 and DE2 Development and Education Boards. * * * *****************************************************************************/ module Altera_UP_Avalon_RS232 ( // Inputs clk, reset, address, chipselect, byteenable, read, write, writedata, UART_RXD, // Bidirectionals // Outputs irq, readdata, UART_TXD ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ parameter BAUD_COUNTER_WIDTH = 9; parameter BAUD_TICK_INCREMENT = 9'd1; parameter BAUD_TICK_COUNT = 9'd433; parameter HALF_BAUD_TICK_COUNT = 9'd216; parameter TOTAL_DATA_WIDTH = 11; parameter DATA_WIDTH = 8; parameter ODD_PARITY = 1'b1; /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input clk; input reset; input address; input chipselect; input [3:0] byteenable; input read; input write; input [31:0] writedata; input UART_RXD; // Bidirectionals // Outputs output reg irq; output reg [31:0] readdata; output UART_TXD; /***************************************************************************** * Internal wires and registers Declarations * *****************************************************************************/ // Internal Wires wire read_fifo_read_en; wire [7:0] read_available; wire [DATA_WIDTH:0] read_data; wire parity_error; wire write_data_parity; wire [7:0] write_space; // Internal Registers reg read_interrupt_en; reg write_interrupt_en; reg read_interrupt; reg write_interrupt; reg write_fifo_write_en; reg [(DATA_WIDTH - 1):0] data_to_uart; // State Machine Registers /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ /***************************************************************************** * Sequential logic * *****************************************************************************/ always @(posedge clk) begin if (reset == 1'b1) irq <= 1'b0; else irq <= write_interrupt | read_interrupt; end always @(posedge clk) begin if (reset == 1'b1) readdata <= 32'h00000000; else if (chipselect == 1'b1) begin if (address == 1'b0) readdata <= {8'h00, read_available, 6'h00, parity_error, //`IF USE_DATA_WIDTH_7 // 2'h0, //`ELSIF USE_DATA_WIDTH_8 1'b0, //`ENDIF read_data[(DATA_WIDTH - 1):0]}; else readdata <= {8'h00, write_space, 6'h00, write_interrupt, read_interrupt, 6'h00, write_interrupt_en, read_interrupt_en}; end end always @(posedge clk) begin if (reset == 1'b1) read_interrupt_en <= 1'b0; else if ((chipselect == 1'b1) && (write == 1'b1) && (address == 1'b1) && (byteenable[0] == 1'b1)) read_interrupt_en <= writedata[0]; end always @(posedge clk) begin if (reset == 1'b1) write_interrupt_en <= 1'b0; else if ((chipselect == 1'b1) && (write == 1'b1) && (address == 1'b1) && (byteenable[0] == 1'b1)) write_interrupt_en <= writedata[1]; end always @(posedge clk) begin if (reset == 1'b1) read_interrupt <= 1'b0; else if (read_interrupt_en == 1'b0) read_interrupt <= 1'b0; else read_interrupt <= (&(read_available[6:5]) | read_available[7]); end always @(posedge clk) begin if (reset == 1'b1) write_interrupt <= 1'b0; else if (write_interrupt_en == 1'b0) write_interrupt <= 1'b0; else write_interrupt <= (&(write_space[6:5]) | write_space[7]); end always @(posedge clk) begin if (reset == 1'b1) write_fifo_write_en <= 1'b0; else write_fifo_write_en <= chipselect & write & ~address & byteenable[0]; end always @(posedge clk) begin if (reset == 1'b1) data_to_uart <= 1'b0; else data_to_uart <= writedata[(DATA_WIDTH - 1):0]; end /***************************************************************************** * Combinational logic * *****************************************************************************/ assign parity_error = (read_available != 8'h00) ? ((^(read_data[DATA_WIDTH:0])) ^ ODD_PARITY) : 1'b0; assign read_fifo_read_en = chipselect & read & ~address & byteenable[0]; assign write_data_parity = (^(data_to_uart)) ^ ODD_PARITY; /***************************************************************************** * Internal Modules * *****************************************************************************/ Altera_UP_RS232_In_Deserializer RS232_In_Deserializer ( // Inputs .clk (clk), .reset (reset), .serial_data_in (UART_RXD), .receive_data_en (read_fifo_read_en), // Bidirectionals // Outputs .fifo_read_available (read_available), .received_data (read_data) ); defparam RS232_In_Deserializer.BAUD_COUNTER_WIDTH = BAUD_COUNTER_WIDTH, RS232_In_Deserializer.BAUD_TICK_INCREMENT = BAUD_TICK_INCREMENT, RS232_In_Deserializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT, RS232_In_Deserializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT, RS232_In_Deserializer.TOTAL_DATA_WIDTH = TOTAL_DATA_WIDTH, RS232_In_Deserializer.DATA_WIDTH = (DATA_WIDTH + 1); Altera_UP_RS232_Out_Serializer RS232_Out_Serializer ( // Inputs .clk (clk), .reset (reset), .transmit_data ({write_data_parity, data_to_uart}), .transmit_data_en (write_fifo_write_en), // Bidirectionals // Outputs .fifo_write_space (write_space), .serial_data_out (UART_TXD) ); defparam RS232_Out_Serializer.BAUD_COUNTER_WIDTH = BAUD_COUNTER_WIDTH, RS232_Out_Serializer.BAUD_TICK_INCREMENT = BAUD_TICK_INCREMENT, RS232_Out_Serializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT, RS232_Out_Serializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT, RS232_Out_Serializer.TOTAL_DATA_WIDTH = TOTAL_DATA_WIDTH, RS232_Out_Serializer.DATA_WIDTH = (DATA_WIDTH + 1); endmodule
Altera_UP_RS232_Counters.v
/***************************************************************************** * * * Module: Altera_UP_RS232_Counters * * Description: * * This module reads and writes data to the RS232 connectpr on Altera's * * DE1 and DE2 Development and Education Boards. * * * *****************************************************************************/ module Altera_UP_RS232_Counters ( // Inputs clk, reset, reset_counters, // Bidirectionals // Outputs baud_clock_rising_edge, baud_clock_falling_edge, all_bits_transmitted ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ parameter BAUD_COUNTER_WIDTH = 9; parameter BAUD_TICK_INCREMENT = 9'd1; parameter BAUD_TICK_COUNT = 9'd433; parameter HALF_BAUD_TICK_COUNT = 9'd216; parameter TOTAL_DATA_WIDTH = 11; /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input clk; input reset; input reset_counters; // Bidirectionals // Outputs output reg baud_clock_rising_edge; output reg baud_clock_falling_edge; output reg all_bits_transmitted; /***************************************************************************** * Internal wires and registers Declarations * *****************************************************************************/ // Internal Wires // Internal Registers reg [(BAUD_COUNTER_WIDTH - 1):0] baud_counter; reg [3:0] bit_counter; // State Machine Registers /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ /***************************************************************************** * Sequential logic * *****************************************************************************/ always @(posedge clk) begin if (reset == 1'b1) baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}}; else if (reset_counters) baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}}; else if (baud_counter == BAUD_TICK_COUNT) baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}}; else baud_counter <= baud_counter + BAUD_TICK_INCREMENT; end always @(posedge clk) begin if (reset == 1'b1) baud_clock_rising_edge <= 1'b0; else if (baud_counter == BAUD_TICK_COUNT) baud_clock_rising_edge <= 1'b1; else baud_clock_rising_edge <= 1'b0; end always @(posedge clk) begin if (reset == 1'b1) baud_clock_falling_edge <= 1'b0; else if (baud_counter == HALF_BAUD_TICK_COUNT) baud_clock_falling_edge <= 1'b1; else baud_clock_falling_edge <= 1'b0; end always @(posedge clk) begin if (reset == 1'b1) bit_counter <= 4'h0; else if (reset_counters) bit_counter <= 4'h0; else if (bit_counter == TOTAL_DATA_WIDTH) bit_counter <= 4'h0; else if (baud_counter == BAUD_TICK_COUNT) bit_counter <= bit_counter + 4'h1; end always @(posedge clk) begin if (reset == 1'b1) all_bits_transmitted <= 1'b0; else if (bit_counter == TOTAL_DATA_WIDTH) all_bits_transmitted <= 1'b1; else all_bits_transmitted <= 1'b0; end /***************************************************************************** * Combinational logic * *****************************************************************************/ /***************************************************************************** * Internal Modules * *****************************************************************************/ endmodule
Altera_UP_RS232_In_Deserializer.v
/***************************************************************************** * * * Module: Altera_UP_RS232_In_Deserializer * * Description: * * This module reads data to the RS232 UART Port. * * * *****************************************************************************/ module Altera_UP_RS232_In_Deserializer ( // Inputs clk, reset, serial_data_in, receive_data_en, // Bidirectionals // Outputs fifo_read_available, received_data ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ parameter BAUD_COUNTER_WIDTH = 9; parameter BAUD_TICK_INCREMENT = 9'd1; parameter BAUD_TICK_COUNT = 9'd433; parameter HALF_BAUD_TICK_COUNT = 9'd216; parameter TOTAL_DATA_WIDTH = 11; parameter DATA_WIDTH = 9; /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input clk; input reset; input serial_data_in; input receive_data_en; // Bidirectionals // Outputs output reg [7:0] fifo_read_available; output [(DATA_WIDTH - 1):0] received_data; /***************************************************************************** * Internal wires and registers Declarations * *****************************************************************************/ // Internal Wires wire shift_data_reg_en; wire all_bits_received; wire fifo_is_empty; wire fifo_is_full; wire [6:0] fifo_used; // Internal Registers reg receiving_data; reg [(TOTAL_DATA_WIDTH - 1):0] data_in_shift_reg; // State Machine Registers /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ /***************************************************************************** * Sequential logic * *****************************************************************************/ always @(posedge clk) begin if (reset == 1'b1) fifo_read_available <= 8'h00; else fifo_read_available <= {fifo_is_full, fifo_used}; end always @(posedge clk) begin if (reset == 1'b1) receiving_data <= 1'b0; else if (all_bits_received == 1'b1) receiving_data <= 1'b0; else if (serial_data_in == 1'b0) receiving_data <= 1'b1; end always @(posedge clk) begin if (reset == 1'b1) data_in_shift_reg <= {TOTAL_DATA_WIDTH{1'b0}}; else if (shift_data_reg_en) data_in_shift_reg <= {serial_data_in, data_in_shift_reg[(TOTAL_DATA_WIDTH - 1):1]}; end /***************************************************************************** * Combinational logic * *****************************************************************************/ /***************************************************************************** * Internal Modules * *****************************************************************************/ Altera_UP_RS232_Counters RS232_In_Counters ( // Inputs .clk (clk), .reset (reset), .reset_counters (~receiving_data), // Bidirectionals // Outputs .baud_clock_rising_edge (), .baud_clock_falling_edge (shift_data_reg_en), .all_bits_transmitted (all_bits_received) ); defparam RS232_In_Counters.BAUD_COUNTER_WIDTH = BAUD_COUNTER_WIDTH, RS232_In_Counters.BAUD_TICK_INCREMENT = BAUD_TICK_INCREMENT, RS232_In_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT, RS232_In_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT, RS232_In_Counters.TOTAL_DATA_WIDTH = TOTAL_DATA_WIDTH; Altera_UP_SYNC_FIFO RS232_In_FIFO ( // Inputs .clk (clk), .reset (reset), .write_en (all_bits_received & ~fifo_is_full), .write_data (data_in_shift_reg[(DATA_WIDTH + 1):1]), .read_en (receive_data_en & ~fifo_is_empty), // Bidirectionals // Outputs .fifo_is_empty (fifo_is_empty), .fifo_is_full (fifo_is_full), .words_used (fifo_used), .read_data (received_data) ); defparam RS232_In_FIFO.DATA_WIDTH = DATA_WIDTH, RS232_In_FIFO.DATA_DEPTH = 128, RS232_In_FIFO.ADDR_WIDTH = 7; endmodule
Altera_UP_RS232_Out_Serializer.v
/***************************************************************************** * * * Module: Altera_UP_RS232_Out_Serializer * * Description: * * This module writes data to the RS232 UART Port. * * * *****************************************************************************/ module Altera_UP_RS232_Out_Serializer ( // Inputs clk, reset, transmit_data, transmit_data_en, // Bidirectionals // Outputs fifo_write_space, serial_data_out ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ parameter BAUD_COUNTER_WIDTH = 9; parameter BAUD_TICK_INCREMENT = 9'd1; parameter BAUD_TICK_COUNT = 9'd433; parameter HALF_BAUD_TICK_COUNT = 9'd216; parameter TOTAL_DATA_WIDTH = 11; parameter DATA_WIDTH = 9; /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input clk; input reset; input [DATA_WIDTH:1] transmit_data; input transmit_data_en; // Bidirectionals // Outputs output reg [7:0] fifo_write_space; output reg serial_data_out; /***************************************************************************** * Internal wires and registers Declarations * *****************************************************************************/ // Internal Wires wire shift_data_reg_en; wire all_bits_transmitted; wire read_fifo_en; wire fifo_is_empty; wire fifo_is_full; wire [6:0] fifo_used; wire [DATA_WIDTH:1] data_from_fifo; // Internal Registers reg transmitting_data; reg [DATA_WIDTH:0] data_out_shift_reg; // State Machine Registers /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ /***************************************************************************** * Sequential logic * *****************************************************************************/ always @(posedge clk) begin if (reset == 1'b1) fifo_write_space <= 8'h00; else fifo_write_space <= 8'h80 - {fifo_is_full, fifo_used}; end always @(posedge clk) begin if (reset == 1'b1) serial_data_out <= 1'b1; else serial_data_out <= data_out_shift_reg[0]; end always @(posedge clk) begin if (reset == 1'b1) transmitting_data <= 1'b0; else if (all_bits_transmitted == 1'b1) transmitting_data <= 1'b0; else if (fifo_is_empty == 1'b0) transmitting_data <= 1'b1; end always @(posedge clk) begin if (reset == 1'b1) data_out_shift_reg <= {(DATA_WIDTH + 1){1'b1}}; else if (read_fifo_en) data_out_shift_reg <= {data_from_fifo, 1'b0}; else if (shift_data_reg_en) data_out_shift_reg <= {1'b1, data_out_shift_reg[DATA_WIDTH:1]}; end /***************************************************************************** * Combinational logic * *****************************************************************************/ assign read_fifo_en = ~transmitting_data & ~fifo_is_empty & ~all_bits_transmitted; /***************************************************************************** * Internal Modules * *****************************************************************************/ Altera_UP_RS232_Counters RS232_Out_Counters ( // Inputs .clk (clk), .reset (reset), .reset_counters (~transmitting_data), // Bidirectionals // Outputs .baud_clock_rising_edge (shift_data_reg_en), .baud_clock_falling_edge (), .all_bits_transmitted (all_bits_transmitted) ); defparam RS232_Out_Counters.BAUD_COUNTER_WIDTH = BAUD_COUNTER_WIDTH, RS232_Out_Counters.BAUD_TICK_INCREMENT = BAUD_TICK_INCREMENT, RS232_Out_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT, RS232_Out_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT, RS232_Out_Counters.TOTAL_DATA_WIDTH = TOTAL_DATA_WIDTH; Altera_UP_SYNC_FIFO RS232_Out_FIFO ( // Inputs .clk (clk), .reset (reset), .write_en (transmit_data_en & ~fifo_is_full), .write_data (transmit_data), .read_en (read_fifo_en), // Bidirectionals // Outputs .fifo_is_empty (fifo_is_empty), .fifo_is_full (fifo_is_full), .words_used (fifo_used), .read_data (data_from_fifo) ); defparam RS232_Out_FIFO.DATA_WIDTH = DATA_WIDTH, RS232_Out_FIFO.DATA_DEPTH = 128, RS232_Out_FIFO.ADDR_WIDTH = 7; endmodule
Altera_UP_SYNC_FIFO.v
/***************************************************************************** * * * Module: Altera_UP_SYNC_FIFO * * Description: * * This module is a FIFO with same clock for both reads and writes. * * * *****************************************************************************/ module Altera_UP_SYNC_FIFO ( // Inputs clk, reset, write_en, write_data, read_en, // Bidirectionals // Outputs fifo_is_empty, fifo_is_full, words_used, read_data ); /***************************************************************************** * Parameter Declarations * *****************************************************************************/ parameter DATA_WIDTH = 32; parameter DATA_DEPTH = 128; parameter ADDR_WIDTH = 7; /***************************************************************************** * Port Declarations * *****************************************************************************/ // Inputs input clk; input reset; input write_en; input [DATA_WIDTH:1] write_data; input read_en; // Bidirectionals // Outputs output fifo_is_empty; output fifo_is_full; output [ADDR_WIDTH:1] words_used; output [DATA_WIDTH:1] read_data; /***************************************************************************** * Internal wires and registers Declarations * *****************************************************************************/ // Internal Wires // Internal Registers // State Machine Registers /***************************************************************************** * Finite State Machine(s) * *****************************************************************************/ /***************************************************************************** * Sequential logic * *****************************************************************************/ /***************************************************************************** * Combinational logic * *****************************************************************************/ /***************************************************************************** * Internal Modules * *****************************************************************************/ scfifo Sync_FIFO ( // Inputs .clock (clk), .sclr (reset), .data (write_data), .wrreq (write_en), .rdreq (read_en), // Bidirectionals // Outputs .empty (fifo_is_empty), .full (fifo_is_full), .usedw (words_used), .q (read_data) // Unused // synopsys translate_off , .aclr (), .almost_empty (), .almost_full () // synopsys translate_on ); defparam Sync_FIFO.add_ram_output_register = "OFF", Sync_FIFO.intended_device_family = "Cyclone II", Sync_FIFO.lpm_numwords = DATA_DEPTH, Sync_FIFO.lpm_showahead = "ON", Sync_FIFO.lpm_type = "scfifo", Sync_FIFO.lpm_width = DATA_WIDTH, Sync_FIFO.lpm_widthu = ADDR_WIDTH, Sync_FIFO.overflow_checking = "OFF", Sync_FIFO.underflow_checking = "OFF", Sync_FIFO.use_eab = "ON"; endmodule
myfifo.v
// megafunction wizard: %FIFO% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: scfifo // ============================================================ // File Name: myfifo.v // Megafunction Name(s): // scfifo // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 6.0 Build 178 04/27/2006 SJ Full Version // ************************************************************ //Copyright (C) 1991-2006 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module myfifo ( clock, data, rdreq, sclr, wrreq, empty, full, q, usedw); input clock; input [31:0] data; input rdreq; input sclr; input wrreq; output empty; output full; output [31:0] q; output [6:0] usedw; wire [6:0] sub_wire0; wire sub_wire1; wire [31:0] sub_wire2; wire sub_wire3; wire [6:0] usedw = sub_wire0[6:0]; wire empty = sub_wire1; wire [31:0] q = sub_wire2[31:0]; wire full = sub_wire3; scfifo scfifo_component ( .rdreq (rdreq), .sclr (sclr), .clock (clock), .wrreq (wrreq), .data (data), .usedw (sub_wire0), .empty (sub_wire1), .q (sub_wire2), .full (sub_wire3) // synopsys translate_off , .aclr (), .almost_empty (), .almost_full () // synopsys translate_on ); defparam scfifo_component.add_ram_output_register = "OFF", scfifo_component.intended_device_family = "Cyclone II", scfifo_component.lpm_numwords = 128, scfifo_component.lpm_showahead = "ON", scfifo_component.lpm_type = "scfifo", scfifo_component.lpm_width = 32, scfifo_component.lpm_widthu = 7, scfifo_component.overflow_checking = "OFF", scfifo_component.underflow_checking = "OFF", scfifo_component.use_eab = "ON"; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1" // Retrieval info: PRIVATE: Clock NUMERIC "0" // Retrieval info: PRIVATE: Depth NUMERIC "128" // Retrieval info: PRIVATE: Empty NUMERIC "1" // Retrieval info: PRIVATE: Full NUMERIC "1" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" // Retrieval info: PRIVATE: Optimize NUMERIC "2" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" // Retrieval info: PRIVATE: UsedW NUMERIC "1" // Retrieval info: PRIVATE: Width NUMERIC "32" // Retrieval info: PRIVATE: dc_aclr NUMERIC "0" // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" // Retrieval info: PRIVATE: rsFull NUMERIC "0" // Retrieval info: PRIVATE: rsUsedW NUMERIC "0" // Retrieval info: PRIVATE: sc_aclr NUMERIC "0" // Retrieval info: PRIVATE: sc_sclr NUMERIC "1" // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" // Retrieval info: PRIVATE: wsFull NUMERIC "1" // Retrieval info: PRIVATE: wsUsedW NUMERIC "0" // Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128" // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" // Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7" // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" // Retrieval info: CONSTANT: USE_EAB STRING "ON" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] // Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty // Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0] // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq // Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr // Retrieval info: USED_PORT: usedw 0 0 7 0 OUTPUT NODEFVAL usedw[6..0] // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq // Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 // Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 // Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 // Retrieval info: CONNECT: usedw 0 0 7 0 @usedw 0 0 7 0 // Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: GEN_FILE: TYPE_NORMAL myfifo.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL myfifo.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL myfifo.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL myfifo.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL myfifo_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL myfifo_bb.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL myfifo_waveforms.html TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL myfifo_wave*.jpg FALSE
fit.summary
Fitter Status : Successful - Tue Jul 24 14:59:03 2007 Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version Revision Name : rs232lab Top-level Entity Name : rs232lab Family : Cyclone II Device : EP2C35F672C6 Timing Models : Final Total logic elements : 0 / 33,216 ( 0 % ) Total registers : 0 Total pins : 178 / 475 ( 37 % ) Total virtual pins : 0 Total memory bits : 0 / 483,840 ( 0 % ) Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % ) Total PLLs : 0 / 4 ( 0 % )
tan.summary
-------------------------------------------------------------------------------------- Timing Analyzer Summary -------------------------------------------------------------------------------------- Type : Worst-case tpd Slack : N/A Required Time : None Actual Time : 9.719 ns From : SW[15] To : LEDR[15] From Clock : -- To Clock : -- Failed Paths : 0 Type : Total number of failed paths Slack : Required Time : Actual Time : From : To : From Clock : To Clock : Failed Paths : 0 --------------------------------------------------------------------------------------
Maintained by John Loomis, last updated Tue Jul 24 14:59:39 2007