NiosII CPU Development

SRISC 1

isa1 tests the add/sub and logical-operation instructions.

srisc1.zip setup and read instruction memory

de2risc1.zip

References

srisc1 organization
srisc1 project report
instruction ROM waveforms (quartus-generated document)

SRISC 2

srisc2.zip add register file

de2risc2.zip

References

srisc2 organization
srisc2 project summary

SRISC 3

srisc3.zip add ALU

References

srisc3 organization
srisc3 project summary

SRISC 4

isa2 tests the shift and rotate instructions.

srisc4.zip add barrel (logarithmic) shifter

References

srisc4 organization
srisc4 project summary

SRISC 5

isa3 tests the compare instructions.

srisc5.zip add logic for compare instructions

References

srisc5 organization
srisc5 project summary

SRISC 6

isa4 tests the branch instructions.

srisc6.zip implements branch instructions. This version is the first with instructions executed in non-sequential order.

References

srisc6 organization
srisc6 project summary

SRISC 7

isa5 tests the jump instructions.

srisc7.zip implements jump instructions.

References

srisc7 organization
srisc7 project summary

SRISC 8

isa6 tests the 32-bit load/store instructions.

srisc8.zip implements 32-bit load/store instructions.

References

srisc8 organization
srisc8 project summary

SRISC 9

isa7 tests the variable-size load/store instructions.

srisc9.zip implements variable-size load/store instructions.

References

srisc9 organization
srisc9 project summary
memory waveforms (quartus-generated document)

Other Information

Cyclone II size reports


Maintained by John Loomis, last updated 20 October 2008