Altera Nios II Architecture and Programming

A Nios II processor is a 32-bit RISC “computer on a chip” that includes a CPU, a set of on-chip peripherals, onchip memory, and interfaces to off-chip memory, all implemented on a single Altera FPGA chip.

Basic Nios II System

• Nios II Lab 1

  The purpose of this lab is to learn how to create and use a simple reconfigurable computer system. This system uses on-chip memory, and can only host relatively small software projects.

• PIO Example

  This example shows how to use the PIO peripheral, in this case connecting the outputs of the toggle switches through the cpu to the inputs of the seven-segment displays.

• Instruction Set Simulator

  This page shows how to use the Debug capability of the IDE and the Nios II Instruction Set Simulator.

• Nios II Command Shell

  This page shows how to use the Nios II Command Shell (console window).

Machine Instructions

• Arithmetic and Logic Instructions
• Shift Instructions
• Comparison Instructions
• Branch Instructions
• Jump Instructions
• Load/Store Instructions

Assembly Language

• Nios II Assembler/Simulation

Components

• register file
• alu test (signed subtraction)
• barrel shifter

Second Nios II System

• Nios II system with SDRAM
• Startup routines
• Stack and global pointer
• Dhrystone benchmark

Exceptions and Interrupts

• Software exceptions (trap instruction)
• Hardware interrupt example
• Exception and Interrupt Controller
• Control Registers
• Exception Handling

Nios II Reference

• Register usage
• Opcodes
• Pseudo-Instructions

Maintained by John Loomis, last updated 17 November 2008